Alena Simalatsar

metro II: A design environment for cyber-physical systems

Cyber-Physical Systems are integrations of computation and physical processes and as such, will be increasingly relevant to industry and people. The complexity of designing CPS resides in their heterogeneity. Heterogeneity manifest itself in modeling their functionality as well as in the implementation platforms that include a multiplicity of components such as microprocessors, signal processors, peripherals, memories, sensors and actuators often integrated on a single chip or on a small package such as a multi-chip module. We need a methodology, tools and environments where heterogeneity can be dealt with at all levels of abstraction and where different tools can be integrated. We present here Platform-Based Design as the CPS methodology of choice and metroII, a design environment that supports it. We present the metamodeling approach followed in metroII, how to couple the functionality and implementation platforms of CPS, and the simulation technology that supports the analysis of CPS and of their implementation. We also present examples of use and the integration of metroII with another popular design environment developed at Verimag, BIP.

A methodology for power consumption evaluation of wireless sensor networks

Energy consumption is one of the most constraining requirements for the design and implementation of wireless sensor networks. Simulation tools allow one to significantly decrease the effort and time spent to choose the right solution. Existing simulators provide varying degrees of analysis for communication, application and energy domains. However, they do not provide enough flexibility to estimate the consumed power for a wide range of wireless sensor network (WSN) hardware (HW) platforms. In this paper we present a flexible and extensible simulation framework to estimate power consumption of sensor network applications for arbitrary HW platforms. This framework allows designers of sensor networks to estimate power consumption of the explored HW platform which permits the selection of an optimal HW solution and software (SW) implementation for the desired projects.

Enabling parametric feasibility analysis in real-time calculus driven performance evaluation

This paper advocates a rigorously formal and compositional style for obtaining key performance and/or interface metrics of systems with real-time constraints. We propose a hierarchical approach that couples the independent and different by nature frameworks of Modular Performance Analysis with Real-time Calculus (MPARTC) and Parametric Feasibility Analysis (PFA). Recent work on Real-time Calculus (RTC) has established an embedding of state-based component models into RTC-driven performance analysis for dealing with more expressive component models. However, with the obtained analysis infrastructure it is possible to analyze components only for a fixed set of parameters, e. g., fixed CPU speeds, fixed buffer sizes etc., such that a big space of parameters remains unstudied. In this paper, we overcome this limitation by integrating the method of parametric feasibility analysis in an RTC-based modeling environment. Using the PFA tool-flow, we are able to find regions for component parameters that maintain feasibility and worst-case properties. As a result, the proposed analysis infrastructure produces a broader range of valid design candidates, and allows the designer to reason about the system robustness.

A methodology for architecture exploration and performance analysis using system level design languages and rapid architecture profiling

The implementation of service-rich, highly interconnected applications and the increasing demand for performance, requires the development of highly optimized and flexible computing platforms. However, the tight real-time requirements of such systems, together with constraints on cost and physical size of the devices, results in increased design complexity and system heterogeneity. This creates a large design space. In this paper, we propose a structured approach based on system level specification languages that supports the rapid exploration and performance evaluation of computing platforms, including their middleware components, through simulation of abstract models. Accuracy is achieved through an off-line rapid architecture profiling procedure. We focus on a process network model, which is more suitable to the description of concurrent functions and data-dominated applications than a traditional sequential programming model. We describe the structure of our simulation framework, and use it to evaluate the performance of the lower layers of the UMTS protocol when mapped on software defined radio oriented architectures.

TAT-based formal representation of medical guidelines: Imatinib case-study

Computer-based interpretation of medical guidelines (GLs) has drawn lots of attention in the past three decades. It is essential to use a formalism for GLs representation that would enable the validation of GLs structural properties, be able to map medical actions into the time scale and support the automatic formal verification of GLs without additional translation paths. In this paper we preset a novel approach based on Timed Automata extended with Tasks (TAT) for the medical protocol formal representation using the TIMES toolbox. We discuss the verification issues with the help of the Imatinib case study.

Parameterized SVM for personalized drug concentration prediction

This paper proposes a parameterized Support Vector Machine (ParaSVM) approach for modeling the Drug Concentration to Time (DCT) curves. It combines the merits of Support Vector Machine (SVM) algorithm that considers various patient features and an analytical model that approximates the predicted DCT points and enables curve calibrations using occasional real Therapeutic Drug Monitoring (TDM) measurements. The RANSAC algorithm is applied to construct the parameter library for the relevant basis functions. We show an example of using ParaSVM to build DCT curves and then calibrate them by TDM measurements on imatinib case study.

Representation of Medical Guidelines with a Computer Interpretable Model

Nowadays medical software is tightly coupled with medical devices that perform patient state monitoring and lately even some basic treatment procedures. Medical guidelines (GLs) can be seen as specification of a medical system which requires their computer-interpretable representation of medical GLs. Until now most of the medical GLs are often represented in a textual format and therefore often suffer from such structural problems as incompleteness, inconsistencies, ambiguity and redundancy, which makes the translation process to the machine-interpretable language more complicated. Computer-based interpretation of GLs can improve the quality of protocols as well as the quality of medical service. Several GLs formal representation methods have been presented recently. Only some of them enable automatic formal verification by introducing an additional translation path to the existing model checking environments. However, if a verified property fails it is difficult to trace back the result needed to change the model. Moreover, these formalisms provide the notion of time mostly in terms of actions order. In this paper we preset the application of a well-know formal behaviour representation approach of embedded systems design domain to medical GLs interpretation. We use Timed Automata extended with Tasks (TAT) and TIMES toolbox to represent medical GLs as a system behaviour in a computer interpretable form. We discuss the verification issues with the help of the anticancer drug imatinib case study.

UMTS MPSoC design evaluation using a system level design framework

Rapid design space exploration with accurate models is necessary to improve designer productivity at the electronic system level. We describe how to use a new event-based design framework, Metro II, to carry out simulation and design space exploration of multi-core architectures. We illustrate the design methodology on a UMTS data link layer design case study with both a timed and untimed functional model as well as a complete set of MPSoC architectural services. We compare different architectures (including RTOSes) explored with Metro II and quantify the associated simulation overhead.

Medical guidelines reconciling medical software and electronic devices: Imatinib case-study

Nowadays medical software is tightly coupled with medical devices that perform patient state monitoring and lately even some basic treatment procedures. Medical guidelines (GLs) can be seen as specification of a medical system that includes both software and electronic devices. However, often medical GLs suffer from structural problems, such as incompleteness, inconsistencies, ambiguity and redundancy. Formal representation of GLs would enable the validation of GLs structural, real-time and life-cycle properties. Several GLs formal representation methods have been presented recently. Only some of them enable automatic formal verification by introducing an additional translation path to the existing model checking environments. However, if a verified property fails it is difficult to trace back the result needed to change the model. Moreover, these formalisms provide the notion of time mostly in terms of actions order. In this paper we preset a novel approach based on Timed Automata extended with Tasks (TAT) for the medical protocol formal representation using the TIMES toolbox. We discuss the verification issues with the help of the Imatinib case study.

Worst-Case Execution Time Analysis for Many-Core Architectures with NoC

The optimal deployment of data streaming applications onto multi-/many-core platforms providing real-time guarantees requires to solve the application partitioning/placement, buffer allocation, task mapping and scheduling optimisation problem using the tasks Worst-Case Execution Time (WCET). In turn, task WCET varies due to interferences that tasks experience when accessing shared resources, which vary depending on the solutions of the optimisation problem. To break this cyclic dependency we propose a detailed interference-based method that first over-approximates WCET based on the solution for application partitioning/placement and then tightens it by pruning out the interferences from tasks not overlapping in memory access and time. We prove that the derived bounds are safe. We have found that interferences on average amount to 10 % of WCET, and were able to improve the latency-guarantee up to 34 %.