Giovanni De Micheli

System-level power optimization: techniques and tools

This tutorial presents a cohesive view of power-conscious system-level design. We consider systems as consisting of a hardware platform executing software programs. We address the problems of power estimation and minimization for such systems. We consider the major constituents of systems: processors, memories and communication resources. We analyze power dissipation in these components and we survey computer-aided power reduction techniques. We also consider global system-level control schemes, such as dynamic power management. We conclude by pointing out further research problems which are still open in this domain.

Analysis of power consumption on switch fabrics in network routers

In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, internal buffers and interconnect wires inside switch fabric architectures. A simulation platform is also implemented to trace the dynamic power consumption with bit-level accuracy. Using this framework, four switch fabric architectures are analyzed under different traffic throughput and different numbers of ingress/egress ports. This framework and analysis can be applied to the architectural exploration for low power high performance network router designs.

×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip

Future Systems on Chips (SoCs) will integrate a large number of processor and storage cores onto a single chip and require Networks on Chip (NoC) to support the heavy communication demands of the system. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication infrastructure should optimally match communication patterns among these components accounting for the individual component needs. In this paper we present xpipes Compiler, a tool for automatically instantiating an application-specific NoC for heterogeneous Multi-Processor SoCs. The xpipes Compiler instantiates a network of building blocks from a library of composable soft macros (switches, network interfaces and links) described in SystemC at the cycle-accurate level. The network components are optimized for that particular network and support reliable, latency-insensitive operation. Example systems with application-specific NoCs built using the xpipes Compiler show large savings in area (factor of 6.5), power (factor of 2.4) and latency (factor of 1.42) when compared to a general-purpose mesh-based NoC architecture.

Dynamic power management for portable systems

Portable systems require long battery lifetime while still delivering high performance. Dynamic power management (DPM) policies trade off the performance for the power consumption at the system level in portable devices. In this work we present the time-indexed SMDP model (TISMDP) that we use to derive optimal policy for DPM in portable systems. TISMDP model is needed to handle the non-exponential user request interarrival times we observed in practice. We use our policy to control power consumption on three different devices: the SmartBadge portable device [18], the Sony Vaio laptop hard disk and WLAN card. Simulation results show large savings for all three devices when using our algorithm. In addition, we measured the power consumption and performance of our algorithm and compared it with other DPM algorithms for laptop hard disk and WLAN card. The algorithm based on our TISMDP model has 1.7 times less power consumption as compared to the default Windows timeout policy for the hard disk and three times less power consumption as compared to the default algorithm for the WLAN card.

Synchronous versus asynchronous modeling of gene regulatory networks

Motivation: In silico modeling of gene regulatory networks has gained some momentum recently due to increased interest in analyzing the dynamics of biological systems. This has been further facilitated by the increasing availability of experimental data on gene–gene, protein–protein and gene–protein interactions. The two dynamical properties that are often experimentally testable are perturbations and stable steady states. Although a lot of work has been done on the identification of steady states, not much work has been reported on in silico modeling of cellular differentiation processes. Results: In this manuscript, we provide algorithms based on reduced ordered binary decision diagrams (ROBDDs) for Boolean modeling of gene regulatory networks. Algorithms for synchronous and asynchronous transition models have been proposed and their corresponding computational properties have been analyzed. These algorithms allow users to compute cyclic attractors of large networks that are currently not feasible using existing software. Hereby we provide a framework to analyze the effect of multiple gene perturbation protocols, and their effect on cell differentiation processes. These algorithms were validated on the T-helper model showing the correct steady state identification and Th1–Th2 cellular differentiation process. Availability: The software binaries for Windows and Linux platforms can be downloaded from http://si2.epfl.ch/~garg/genysis.html. Contact: abhishek.garg@epfl.ch

Prediction of regulatory modules comprising microRNAs and target genes

MOTIVATION MicroRNAs (miRNAs) are small endogenous RNAs that can play important regulatory roles via the RNA-interference pathway by targeting mRNAs for cleavage or translational repression. We propose a computational method to predict miRNA regulatory modules (MRMs) or groups of miRNAs and target genes that are believed to participate cooperatively in post-transcriptional gene regulation. RESULTS We tested our method with the human genes and miRNAs, predicting 431 MRMs. We analyze a module with genes: BTG2, WT1, PPM1D, PAK7 and RAB9B, and miRNAs: miR-15a and miR-16. Review of the literature and annotation with Gene Ontology terms reveal that the roles of these genes can indeed be closely related in specific biological processes, such as gene regulation involved in breast, renal and prostate cancers. Furthermore, it has been reported that miR-15a and miR-16 are deleted together in certain types of cancer, suggesting a possible connection between these miRNAs and cancers. Given that most known functionalities of miRNAs are related to negative gene regulation, extending our approach and exploiting the insight thus obtained may provide clues to achieving practical accuracy in the reverse-engineering of gene regulatory networks. AVAILABILITY A list of predicted modules is available from the authors upon request.

High level synthesis of ASICs under timing and synchronization constraints

This invention is directed to a window shade cutter for manually trimming the end of a rolled shade to conform to the size of the window opening into which the shade is to be mounted. The cutter includes a cylindrical clamping sleeve, having an annular guide groove at one end thereof, adapted to slip over the shade and clamp in place and a cutoff tool receivable in the guide groove including a generally planar U-shaped holder and a planar blade mounted on the holder. In a preferred form, the blade has a rounded, dull end with a central V-shaped notch therein in which a pair of cutting edges are located. The cutoff tool is adapted to interlock in the guide groove and to rotate about the shade with cutting of the shade taking place in the V-shaped notch a few layers at a time as the tool is urged towards the shade and rotated. In accordance with the invention disclosed, window shades can be safely and easily trimmed by the consumer in the home thus eliminating the need for cutting machines.

Quantitative comparison of power management algorithms

Dynamic power management saves power by shutting down idle devices. Several management algorithms have been proposed and demonstrated to be effective in certain applications. We quantitatively compare the power saving and performance impact of these algorithms on hard disks of a desktop and notebook computers. This paper has three contributions. First, we build a framework in Windows NT to implement power managers running realistic workloads and directly interacting with users. Second, we define performance degradation that reflects user perception. Finally, we compare power saving and performance of existing algorithms and analyze the difference.

Packetization and routing analysis of on-chip multiprocessor networks

Some current and most future systems-on-chips use and will use network architectures/protocols to implement on-chip communication. On-chip networks borrow features and design methods from those used in parallel computing clusters and computer system area networks. They differ from traditional networks because of larger on-chip wiring resources and flexibility, as well as constraints on area and energy consumption (in addition to performance requirements). In this paper, we analyze different routing schemes for packetized on-chip communication on a mesh network architecture, with particular emphasis on specific benefits and limitations of silicon VLSI implementations. A contention-look-ahead on-chip routing scheme is proposed. It reduces the network delay with significantly smaller buffer requirement. We further show that in the on-chip multiprocessor systems, both the instruction execution inside node processors, as well as data transaction between different processing elements, are greatly affected by the packetized dataflows that are transported on the on-chip networks. Different packetization schemes affect the performance and power consumption of multiprocessor systems. Our analysis is also quantified by the network/multiprocessor co-simulation benchmark results.

×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips

The limited scalability of current bus topologies for systems on chips (SoCs) dictates the adoption of networks on chips (NoCs) as a scalable interconnection scheme. Current SoCs are highly heterogeneous in nature, denoting homogeneous, preconfigured NoCs as inefficient drop-in alternatives. While highly parametric, fully synthesizeable (soft) NoC building blocks appear as a good match for heterogeneous MPSoC architectures, the impact of instantiation-time flexibility on performance, power and silicon cost has not yet been quantified. The paper details /spl times/pipes Lite, a design flow for automatic generation of heterogeneous NoCs. /spl times/pipes Lite is based on highly customizable, high frequency and low latency NoC modules, that are fully synthesizeable. Synthesis results provide modules that are directly comparable, if not better, than the current published state-of-the-art NoCs in terms of area, power latency and target operating frequency measurements.