Alessandro Bogliolo

A survey of design techniques for system-level dynamic power management

Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited). In this paper, we survey several approaches to system-level dynamic power management. We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption. We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components.

MPARM: Exploring the Multi-Processor SoC Design Space with SystemC

Technology is making the integration of a large number of processors on the same silicon die technically feasible. These multi-processor systems-on-chip (MP-SoC) can provide a high degree of flexibility and represent the most efficient architectural solution for supporting multimedia applications, characterized by the request for highly parallel computation. As a consequence, tools for the simulation of these systems are needed for the design stage, with the distinctive requirement of simulation speed, accuracy and capability to support design space exploration. We developed a complete simulation platform for a MP-SoC called MP-ARM, based on SystemC as modelling and simulation environment, and including models for processors, the AMBA bus compliant communication architecture, memory models and support for parallel programming. A fully operating linux version for embedded systems has been ported on this platform, and a cross-toolchain has been developed as well. Our MP simulation environment turns out to be a powerful tool for the MP-SOC design stage. As an example thereof, we use our tool to evaluate the impact on system performance of architectural parameters and of bus arbitration policies, showing that the effectiveness of a particular system configuration strongly depends on the application domain and the generated traffic profile.

Policy optimization for dynamic power management

Dynamic power management schemes (also called policies) can be used to control the power consumption levels of electronic systems, by setting their components in different states, each characterized by a performance level and a power consumption. In this paper, we describe power-managed systems using a finite-state, stochastic model. Furthermore, we show that the fundamental problem of finding an optimal policy which maximizes the average performance level of a system, subject to a constraint on the power consumption, can be formulated as a stochastic optimization problem called policy optimization. Policy optimization can be solved exactly in polynomial time (in the number of states of the model). We implemented a policy optimization tool and tested the quality of the optimal policies on a realistic case study.

Energetic sustainability of routing algorithms for energy-harvesting wireless sensor networks

A new class of wireless sensor networks that harvest power from the environment is emerging because of its intrinsic capability of providing unbounded lifetime. While a lot of research has been focused on energy-aware routing schemes tailored to battery-operated networks, the problem of optimal routing for energy harvesting wireless sensor networks (EH-WSNs) has never been explored. The objective of routing optimization in this context is not extending network lifetime, but maximizing the workload that can be autonomously sustained by the network. In this work we present a methodology for assessing the energy efficiency of routing algorithms for networks whose nodes drain power from the environment. We first introduce the energetic sustainability problem, then we define the maximum energetically sustainable workload (MESW) as the objective function to be used to drive the optimization of routing algorithms for EH-WSNs. We propose a methodology that makes use of graph algorithms and network simulations for evaluating the MESW starting from a network topology, a routing algorithm and a distribution of the environmental power available at each node. We present a tool flow implementing the proposed methodology and we show comparative results achieved on several routing algorithms. Experimental results highlight that routing strategies that do not take into account environmental power do not provide optimal results in terms of workload sustainability. Using optimal routing algorithms may lead to sizeable enhancements of the maximum sustainable workload. Moreover, optimality strongly depends on environmental power configurations. Since environmental power sources change over time, our results prompt for a new class of routing algorithms for EH-WSNs that are able to dynamically adapt to time-varying environmental conditions.

DNA detection by integrable electronics

This paper presents a new electronic methodology to detect DNA hybridization for rapid identification of diseases, as well as food and environmental monitoring on a genetic base. The proposed solution exploits a new (electrical) capacitive measurement circuit, not requiring any prior labeling of the DNA (as it is often the case with the commonly employed optical detection). The sensitivity, the reliability, and the reproducibility of this device have been evaluated by experiments performed with a (non-integrated) prototype implementation, easily integrable in IC and/or micro-fabricated lab-on-a-chip.

Clock skew optimization for peak current reduction

The presence of large current peaks on the power and ground lines is a serious concern for designers of synchronous digital circuits. Current peaks are caused by the simultaneous switching of highly loaded clock lines and by the signal propagation through the sequential logic elements. In this work we propose a methodology for reducing the amplitude of the current peaks. This result is obtained by clock skew optimization. We propose an algorithm that, for a given clock cycle time, determines the clock arrival time at each flip-flop in order to minimize the current peaks while respecting timing constraint. Our results on benchmark circuits show that current peaks can be reduced without penalty on cycle time and average power dissipation. Our methodology is therefore well-suited for low-power systems with reduced supply voltage, where low noise margins are a primary concern.

Monitoring system activity for OS-directed dynamic power management

We describe a workload monitoring system that has been specifically designed for supporting dynamic power management in personal computers with tight power constraints (such as laptop or notebook computers). Our monitoring system is minimally intrusive, and has negligible impact on system activity. Moreover, it can be used both for on-line system monitoring and off-line data collection. We used our monitoring tool to collect data on the usage of system resources (disks, CPU, keyboard and mouse) for a laptop computer, under several workload conditions. Our analysis shows that resource usage is strongly resource and workload dependent, and that on-line usage monitoring capability is a critical issue of the implementation of effective power management policies.

System-level dynamic power management

We introduce the design methodology known as dynamic power management (DPM), targeting the maximization of power efficiency under performance constraints for electronic systems. We first describe the basic motivations for implementing DPM, then we survey several power management schemes. Finally, we provide guidelines to assessing the potential impact of a DPM scheme for a given target system.

Regression-based RTL power modeling

Register-transfer level (RTL) power estimation is a key feature for synthesis-based design flows. The main challenge in establishing a sound RTL power estimation methodology is the construction of accurate, yet efficient, models of the power dissipation of functional macros. Such models should be automatically built, and should produce reliable average power estimates. In this paper we propose a general methodology for building and tuning RTL power models. We address both hard macros (presynthesized functional blocks)and soft macros (functional units for which only a synthesizable HDL description is provided). We exploit linear regression and its nonparametric extensions to express the dependency of power dissipation on input and output activity. Bottom-up off-line characterization of regression-based power macromodels is discussed in detail. Moreover, we introduce a low overhead on-line characterization method for enhancing the accuracy of off-line characterization.

Performance Analysis of Arbitration Policies for SoC Communication Architectures

As technology scales toward deep submicron, the integration of a large number of IP blocks on the same silicon die is becoming technically feasible, thus enabling large-scale parallel computations, such as those required for multimedia workloads. The communication architecture is becoming the bottleneck for these multiprocessor Systems-on-Chip (SoC), and efficient contention resolution schemes for managing simultaneous access requests to the shared communication resources are required to prevent system performance degradation. The contribution of this work is to analyze the impact on multiprocessor SoC performance of different bus arbitration policies under different communication patterns, showing the distinctive features of each policy and the strong correlation of their effectiveness with the communication requirements of the applications. Beyond traditional arbitration schemes such as round robin and TDMA, another policy is considered that periodically allocates a temporal slot for contention-free bus utilization to a processor which needs fixed predictable bandwidth for the correct execution of its time-critical task. The results are derived on a complete and scalable multiprocessor SoC simulation platform based on SystemC, whose software support includes a complete embedded multiprocessor OS (RTEMS). The communication architecture is AMBA compliant, and we exploit the flexibility of this multi-master commercial standard, which does not specify the arbitration algorithm, to implement the explored contention resolution schemes.