B. Ricco

Transport properties of polycrystalline silicon films

The transport properties of polycrystalline silicon films are examined and interpreted in terms of a modified grain‐boundary trapping model. The theory has been developed on the assumption of both a δ‐shaped and a uniform energy distribution of interface states. A comparison with experiments indicates that the interface states are nearly monovalent and peaked at midgap. Their density is 3.8×1012 cm−2, in accordance with carrier‐lifetime measurements performed on CVD films.

High-field-induced degradation in ultra-thin SiO/sub 2/ films

Very thin thermal oxides are shown to exhibit a failure mode that is undetected by conventional breakdown tests. This failure mode appears in the form of excessive leakage current at low field and is induced by high-field stresses. The stress-induced oxide leakage is permanent and stable with time and thermal annealing. It becomes the dominant failure mode of thin oxides because it always precedes destructive breakdown. Experimental results and theoretical calculations show that the leakage current is not caused by positive charge generation and accumulation in the oxide. It is proposed that the oxide leakage originates from localized defect-related weak spots where the insulator has experienced significant deterioration from electrical stress. The leakage conduction mechanism appears to be thermally assisted tunneling through the locally reduced injection barrier, and the model seems to be consistent with both I-V measurements at temperatures from 77 K to 250 degrees C and theoretical calculations. >

Nonvolatile multilevel memories for digital applications

When thinking of semiconductor memories, it comes naturally to associate stored bits and memory cells with a one-to-one relationship. That, however, is not really a must nor necessarily the most convenient solution for data storage, since using analog signals and digital-to-analog (D/A) as well as analog-to digital (A/D) conversions a large number of bits could be memorized in a single cell, although, of course, the use of analog signals presents all drawbacks of signal-to-noise ratio that are so well known in electronics. In fact, the real question in this sense concerns the number of bits used for the A/D and D/A conversions, since the conventional (fully) digital case can be seen as the simplest realization of a general approach tending to infinitely precise analog storage (i.e. an infinite number of stored bits per cell) at the other extreme. Naturally, in the real world the conflicting aspects of density (measured in bits per cell) and noise immunity (in a general sense) should be traded off one against the other looking for optimum use of silicon area, of course depending on technology, architectures, circuits and reliability. From this point of view it is obvious that the fully digital approach based on the one-bit one-cell concept does not represent necessarily the best solution. Recently, this general question has assumed real and practical significance for nonvolatile memories, since devices storing two bits per cell are now being introduced on the market. At the same time, in a number of research labs a significant effort is currently being dedicated to the study of the limits and practical convenience of storage density considering the current state of the art in technology and circuit designs. This problem, however, presents a number of interacting aspects concerning cell concept, programming and reading schemes, and architectures and reliability that are of interest well beyond the field of nonvolatile memories, because they are ultimately dealing with the basic question of analog versus digital signals. In this contrast, the present paper considers the question of multilevel nonvolatile memories in all its interacting aspects, analyzing both the current state of the art and the future possibilities.

Modeling and simulation of stress-induced leakage current in ultrathin SiO/sub 2/ films

This paper presents a new model fur stress-induced leakage current (SILC) in ultrathin SiO/sub 2/ films, that is able to explain and accurately represent the experimental data obtained with MOS capacitors fabricated with different technologies and oxide thickness in the 3-7 nm range.

Estimate of signal probability in combinational logic networks

Two methods for the calculation of node signal probabilities in combinational networks are presented. These techniques provide a better accuracy than existing algorithms and a deeper insight in the effects of first-order correlations due to multiple fan-out reconvergences. The proposed algorithms are shown to compare favorably with existing procedures in the analysis of significant benchmarks, both in accuracy and in computational efficiency.<<ETX>>

CMOS DNA Sensor Array With Integrated A/D Conversion Based on Label-Free Capacitance Measurement

This paper presents a fully electronic label-free DNA chip in 0.5-mum CMOS technology, with 5-V supply voltage, suitable for low-cost highly integrated applications. The chip features an array of 128 sensor sites with gold electrodes and integrated measurement, conditioning, multiplexing and analog-to-digital conversion circuitry. The circuits measure capacitance variations due to DNA hybridization on the gold electrodes which are bio-modified by covalently attaching probes of known sequence. Specificity, repeatability and parallel detection capability of the fabricated chip are successfully demonstrated

DNA detection by integrable electronics

This paper presents a new electronic methodology to detect DNA hybridization for rapid identification of diseases, as well as food and environmental monitoring on a genetic base. The proposed solution exploits a new (electrical) capacitive measurement circuit, not requiring any prior labeling of the DNA (as it is often the case with the commonly employed optical detection). The sensitivity, the reliability, and the reproducibility of this device have been evaluated by experiments performed with a (non-integrated) prototype implementation, easily integrable in IC and/or micro-fabricated lab-on-a-chip.

Resonant tunneling of holes in AlAs‐GaAs‐AlAs heterostructures

We have observed resonant tunneling of holes through double‐barrier AlAs‐GaAs‐AlAs structures sandwiched between p+‐GaAs regions. The resonances appeared as negative resistance regions in the current‐voltage characteristics perpendicular to the interface planes. A set of resonant structures was already visible at high temperatures (T≂250 K) while an additional set was observable only at low temperatures (T≤100 K). Although in principle the sets can be attributed to tunneling of light and heavy holes, respectively, an analysis of the number and relative voltage position of the resonances suggests that considerable band mixing occurs. The application of a strong magnetic field, parallel to the tunneling current, introduced shifts in the resonances which support that interpretation.

Scaling the MOS transistor below 0.1 /spl mu/m: methodology, device structures, and technology requirements

This work is a systematic investigation of the feasibility of MOSFETs with a gate length below 0.1 /spl mu/m. Limits imposed on the scalability of oxide thickness and supply voltage require a new scaling methodology which allows these parameters to be maintained constant. The feasibility of achieving sub-0.1 /spl mu/m MOSFETs in this way is evaluated through simulations of the electrical characteristics of several different device structures and by addressing the most important issues related to the scaling down to ultra-short gate lengths. This study forms a valuable starting point for the understanding of technological requirements for future ULSI. >

Quantum-mechanical modeling of accumulation layers in MOS structure

An original method is used for the quantum-mechanical modeling of n-type silicon accumulation layers. Unlike previous methods, which were only valid near 4.2 K, the approach is valid up to room temperature and beyond. The self-consistent results obtained are compared with those of the standard classical model for the accumulation layer, and the differences between them are found to be relevant for the modeling of important device applications. The dependences of the accumulation voltage drop and effective F-N (Fowler-Nordheim) barrier height on oxide electric field and substrate dopine are reported. Experimental F-N current-voltage characteristics of production-quality MOS capacitors are used to validate the quantum results and to show that the standard classical model is not adequate even if the barrier height is considered as a fitting parameter. Approximate analytical expressions giving the semiconductor voltage drop and the effective F-N barrier height as a function of oxide field and substrate doping are derived for and n-type silicon at 77 and 300 K. >