Alessandro Zorat

Accuracy Analysis and Enhancement of DFT-Based Synchrophasor Estimators in Off-Nominal Conditions

Synchrophasor estimation accuracy is a well-known critical issue in systems for smart grid monitoring and control. This paper deals with an in-depth analysis of the effect of both steady-state and dynamic disturbances on single-cycle and multicycle windowed discrete Fourier transform (DFT)-based synchrophasor estimators. Unlike other qualitative or simulation-based results found in the literature, this work provides two accurate and easy-to-use analytical expressions that can be used to determine the worst case range of variation of the total vector error (TVE) due to off-nominal frequency deviations. In such conditions, estimation accuracy is limited by two factors, i.e., the infiltration caused by the input signal image frequency and the scalloping loss associated with the spectrum main lobe of the chosen window. Starting from the aforementioned general analysis, a new two-term window minimizing the detrimental effects of image frequency tone is proposed. The accuracy of the related DFT-based synchrophasor estimator is evaluated under both static and dynamic conditions, which is the most interesting scenario for future smart grids. Moreover, the effect of waveform frequency measurement uncertainty on scalloping loss compensation is quantified. Several simulation results (including the effects of noise, harmonic distortion, and amplitude and phase modulation) confirm that the proposed window can significantly improve the accuracy achievable with a simple single-cycle DFT estimator. Indeed, TVE values much smaller than 1% can be achieved even in the worst case conditions reported in the standard IEEE C37.118.1-2011, when the frequency waveform deviations are within ±4% of the nominal value. In addition, the proposed solution could be useful to improve the performance of more complex dynamic phasor estimators, e.g., those in which the first- and second-order terms of the phasor Taylor series expansion result from the differences of consecutive DFT-based phasor estimates.

Fuzzy systems and approximation

Abstract The basic motivation of using fuzzy rule-based systems especially for control purposes is to deduce simple and fast approximations of the unknown or too complicated models. Fuzzy rule-based systems have become very popuar because of their transparency and easiness of tuning and modification. Recently, some results concerning the explicit functions implemented by realistic fuzzy controllers presented the class of functions that could be implemented in this way. Some parallel results, on the other hand, attempted to prove that the main advantage of using fuzzy systems was the suitability for approximation with arbitrary accuracy in their universality. The explicit formulas and some very recent theoretical results made it clear however that fuzzy systems were not really good approximators, as realistic fuzzy controllers could generate only very rough approximations of given transference functions. In connection with approximation the question can be asked, whether there is an optimal fineness/roughness of a fuzzy rule-base that controls a certain action with roughness gives minimal time complexity. As an example, a target tracking problem was chosen (“Cat and Mouse”, or “Hawk and Sparrow” problem) where the antagonistic criteria of minimizing inference time by the given rule-base and minimizing action time (search for the target, with given uncertainty provided by the rule model) were examined. Under certain assumptions the solution of this optimization problem leads to nontrivial rule-base sizes. These results have also practical applicability since if a fine enough model of the system is known it is always possible to generate a rougher version of the same, by applying the model transformation technique offered by rule interpolation with α-levels.

Totem:. a Highly Parallel Chip for Triggering Applications with Inductive Learning Based on the Reactive Tabu Search

The training of a Multi-Layer Perceptron (MLP) classifier is considered as a Combinatorial Optimization task and solved using the Reactive Tabu Search (RTS) method. RTS needs only forward passes (no derivatives) and does not require high precision network parameters. TOTEM, a special-purpose VLSI chip, was developed to take advantage of the limited memory and processing requirements of RTS: the final system effects a very close match between hardware and training algorithm. The RTS algorithm and the design of TOTEM are discussed, together with the operational characteristics of the VLSI chip and some preliminary training and generalization tests on triggering tasks.

Advances in the design of the TOTEM neurochip

Abstract The TOTEM neurochip has proved its viability as a system for real-time computation in HEP and space applications requiring high performance for event classification, data mining, and signal processing. ISA and VME boards integrating the TOTEM chip as a coprocessor have been made available to selected experimental groups which reported satisfactory results. This paper presents a new architectural solution yielding higher performance and reduced silicon area. The on-chip computational structures have been entirely redesigned to take advantage of a novel approach to number representation that, at the cost of a provably bounded approximation, leads to a much-reduced silicon area, lower power dissipation, and faster computation. This approach is validated by simulation results on experimental data, as presented in the paper.

A digital vision sensor

Abstract This paper presents a monolithic 128 × 128 pixel optical sensor with analog-to-digital converters, control and interface circuits designed specifically for direct connection to a host processor. The structure of the sensor leads to a reduction in the global complexity of the image-acquisition hardware and to the replacement of the noise-prone analog line between sensor and host computer. Simplicity of use is maximized thanks to the encapsulation of all the critical analog components within the chip. The key to the high integration level of the sensor is its implementation in standard CMOS technology, which offers the possibility of integrating signal-conditioning and interface functions on the same die as the sensor array and dispensing with the complex clocking schemes at non-standard voltages required by conventional CCD sensors. Several features convenient in many machine-vision applications are included: square pixels, non-interlaced operation, adjustable sensitivity to light, acquisition of a frame of data on demand and extraction of a region-of-interest by addressing a sub-block of the complete array. A complement of registers is included to control the operational parameters: integration time, analog-to-digital converter resolution and the coordinates of the region of interest. Single 5 V operation is provided. The sensor is fabricated in a 2 μm CMOS process and its functionality at up to 25 frames s -1 has been demonstrated.

An Adaptive Fuzzy Control Module for Automatic Dialysis

This paper presents a fuzzy adaptive control technique to automate the dialysis procedure. The main points of this research are: use of a data base of fuzzy inference rules to formalize the medical experience, use of pre-processed lookup tables to speed up the computation and to allow for run-time changes of the inference rules, implementation of adaptive concept by means a set of performance tables, and — finally — the smooth blending of different control actions to obtain a single output action.

Accuracy of DFT-based synchrophasor estimators at off-nominal frequencies

The accuracy of synchrophasor estimators is a well-known critical issue in systems for smart grid monitoring and control. This paper presents an in-depth analysis of the effect of off-nominal frequency deviations on single-cycle and multi-cycle DFT-based synchrophasor estimators. Unlike other qualitative or simulation-based results available in the literature, this work provides some accurate and easy-to-use expressions that can be used to keep the total vector error within given target uncertainty boundaries.

FPGA Implementation of Support Vector Machines with Pseudo-Logarithmic Number Representation

Computations in Support Vector Machines (SVM) involve a large number of vector multiplications. When implementing such architectures on a stand alone, embedded system, the complexity of the hardware implementation of the multipliers can be a limiting factor. This paper proposes a representation of numerical data to be processed by an approximation of the logarithm of the number, thus allowing the substitution of expensive multipliers with simpler adders. Additional circuitry is proposed to translate between standard and the proposed pseudo-logarithmic number representation. The operations for the representation translation, addition and multiplication with pseudo-logarithmic numbers have been implemented in software and several experiments have been carried out to assess their performance when used in a SVM-based computational architecture that was used for data classification. The results obtained show that the proposed representation yields an accuracy that is comparable with that obtained by using standard floating point or fixed point number representation.

A parallel processor for neural networks

A deeply-pipelined digital parallel processor for the implementation of Multi-Layer Perceptrons is presented. It employs high-speed limited-precision integer arithmetic and allows good recognition performance in combination with a novel training algorithm. Internal dynamic RAM is provided for storage of the weights. The chip achieves a performance of 600 million multiply-and-accumulate operations per second and requires a silicon area of 70 mm/sup 2/ in a 1.2-/spl mu/m CMOS technology.

Classification of SIP messages by a syntax filter and SVMs

The Session Initiation Protocol (SIP) is at the root of many sessions-based applications such as VoIP and media streaming that are used by a growing number of users and organizations. The increase of the availability and use of such applications calls for careful attention to the possibility of transferring malformed, incorrect, or malicious SIP messages as they can cause problems ranging from relatively innocuous disturbances to full blown attacks and frauds. To this end, SIP messages are analyzed to be classified as “good” or “bad” depending on whether this structure and content are deemed acceptable or not. This paper presents a classifier of SIP messages based on a two stage filter. The first stage uses a straightforward lexical analyzer to detect and remove all messages that are lexically incorrect with reference to the grammar that is defined by the protocol standard. The second stage uses a machine learning approach based on a Support Vector Machine (SVM) to analyze the structure of the remaining syntactically correct messages in order to detect semantic anomalies which are deemed a strong indication of a possibly malicious message. The SVM “learns” the structure of the “good” and “bad” SIP messages through an initial training phase and the SVM thus configured correctly classifies messages produced by a synthetic generator and also “real” SIP messages that have been collected from the communication network at our institution. The preliminary results of such classification look very promising and are presented in the final section of this paper.