Andrea Boni

LVDS I/O interface for Gb/s-per-pin operation in 0.35-/spl mu/m CMOS

This paper presents the design and the implementation of input/output (I/O) interface circuits for Gb/s-per-pin operation, fully compatible with low-voltage differential signaling (LVDS) standard. Due to the differential transmission technique and the low voltage swing, LVDS allows high transmission speeds and low power consumption at the same time. In the proposed transmitter, the required tolerance on the dc output levels was achieved over process, temperature, and supply voltage variations with neither external components nor trimming procedures, by means of a closed-loop control circuit and an internal voltage reference. The proposed receiver implements a dual-gain-stage folded-cascode architecture which allows a 1.2-Gb/s transmission speed with the minimum common-mode and differential voltage at the input. The circuits were implemented in a 3.3-V 0.35-/spl mu/m CMOS technology in a couple of test chips. Transmission operations up to 1.2 Gb/s with random data patterns and up to 2 Gb/s in asynchronous mode were demonstrated. The transmitter and receiver pad cells exhibit a power consumption of 43 and 33 mW, respectively.

Op-amps and startup circuits for CMOS bandgap references with near 1-V supply

The design of bandgap-based voltage references in digital CMOS raises several design difficulties, as the supply voltage is lower than the silicon bandgap in electron volts, i.e., 1.2 V. A current-mode architecture is used in order to address the main issues posed by the low supply, but the implementation of the operational amplifier and of dedicated startup circuits deserves some attention. Even if nonstandard devices such as depletion-mode MOS transistors may be helpful to manage the supply scaling, they are seldom available and poorly characterized. Therefore, they must be avoided in a robust design featuring a high portability. This paper proposes some circuit solutions suitable for very low-supply-voltage operation and addresses the main issues of achieving the correct bias point at the power on. A few bandgap references were implemented in digital 0.35- and 0.18-/spl mu/m technologies featuring a nominal output voltage of about 500 mV and minimum supplies from 1.5 to 0.9 V.

A 10-b 185-MS/s track-and-hold in 0.35-/spl mu/m CMOS

This paper discusses the design and the implementation of a high-speed track-and-hold amplifier in 0.35-/spl mu/m CMOS, featuring 10-b resolution up to 185 MS/s. The implemented folded-cascode input buffer allows a relatively large input range, 1-V/sub pp/ differential, and low harmonic distortion at the same time. The sampler is based oh a switched-source-follower (SSF) architecture with double switch-off action and saturation-mode switches, providing short aperture times and high linearity. A spur-free dynamic range (SFDR) of 63 dB at 185 MS/s was measured with a dual-tone 45-MHz/spl plusmn/250-kHz test signal. The open-loop architecture makes harmonic distortion little sensitive to the input frequency: 10-b resolution is maintained up to 45 MHz with 1 V/sub pp/ and up to 70 MHz with 0.7 V/sub pp/. A suitable hold-mode feedthrough rejection is achieved by means of feedforward cancellation with a MOS capacitor operating in depletion or accumulation. The track-and-hold amplifier consumes 70 mW from a 3.3-V supply.

A CMOS analog frontend for a passive UHF RFID tag

The paper discusses the design of the analog frontend of a passive UHF RFID tag, compatible with ISO/IEC 18000-6b standard. An efficient ESD-protected power retrieving circuit, based on the antenna features, a rectifier bridge and a charge pump, is introduced, as well as an auto-calibrated clock generator. The chip, implemented in a 0.18mum digital CMOS technology, does not need any post-fabrication trimming or external component besides the antenna; according to simulations, a correct communication is achieved at a distance of several meters between reader and tag

System-on-chip microwave radiometer for thermal remote sensing and its application to the forest fire detection

This paper focuses on the opportunities offered by the latest advances in silicon technologies for realizing system-on-chip microwave radiometer. Such a highly integrated, low-cost, radiometer chip could be applied to the environmental remote sensing and, in particular, to the forest fire detection. The feasibility study is carried-out in two steps. First, a proof of the concept is given by means of a discrete-component radiometer operating at 12.65 GHz. This radiometer exploits TV-SAT components such as low-noise down-converter and dish antenna. On-field measurements shows a radiometric contrast (increase of the antenna noise temperature due to the fire with respect to the background) of about 8 K for a wooden fire of 0.38 m 2 placed 30 m away from the antenna. Then, a single-chip 13 GHz radiometer has been designed exploiting a CMOS 90 nm standard process. The sensor is based on a direct-conversion architecture with integrated LNA, Gilbertpsilas cell mixer and PLL frequency synthesizer. The IF chain includes an active (gm-C) low-pass filter and a CMOS square-law detector. The circuit simulations show a total receiver gain of 72 dB, an equivalent input noise temperature of 105 K and an IF bandwidth of 100 MHz.

Low-power GS/s track-and-hold with 10-b resolution at Nyquist in SiGe BiCMOS

The brief presents the design and the implementation of a very-high speed track-and-hold amplifier (THA) for analog-digital converters with high input bandwidth. The THA is based on a half-bridge driving a switched-emitter follower. A lower power consumtpion and a simpler circuit architecture than previously reported bipolar implementations were achieved by means of circuit optimization. In particular, the impact of the aspect ratio of the pMOS current generator in the bridge on the harmonic distortion and on the hold-mode behavior is discussed and modeled. Furthermore, a modification of the cancellation capacitor for feedthrough attenuation, fully compatible with the latest BiCMOS technologies is proposed. The THA was implemented in a 0.8-mum SiGe BiSMOS with 30-GHz fT. It features 10-b resolution at a sampling frequency of 1-GS/s at Nyquist with less than 25 mW of power consumption, from a single 2.7-V power supply

1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-/spl mu/m CMOS

This paper describes the design and the implementation of input-output (I/O) interface circuits for serial data links in the gigabit-per-second range. The cells were implemented in a 3.3-V 0.35-/spl mu/m CMOS technology in a couple of test chips. The transmitter is fully compatible (DC coupling) with 100K positive emitter-coupled logic (PECL) systems and it is based on the voltage-switching principle in order to allow different termination schemes besides the canonical ECL termination, i.e., 50-/spl Omega/ toward (V/sub DD/-2) V. The addition of some circuit techniques such as dynamic biasing and strobed current switching boosts the dynamic performance of the basic voltage-switching scheme and relaxes the requirements for a high bias current and large-size output devices at the same time. Moreover, thanks to the developed reference circuit, using both feedforward and feedback controls, the output levels are within the 100K tolerance over the full range of process, supply voltage, and temperature (PVT) variations without resorting to external components or on-chip trimming. The receiver cell is based on a complementary-differential architecture providing high speed and low error on the duty cycle of the CMOS output signal. The integrated receiver-transmitter chain exhibits a maximum toggle frequency of 1 GHz, while a chip-to-chip transmission link using the developed I/O interface was tested up to 1.2 Gb/s.

A 6-bit, 1.2 GHz Interleaved SAR ADC in 90nm CMOS

A 6-bit time-interleaved analog-to-digital converter for ultra-wide band applications is proposed. The structure consists of seven successive approximation A/D converters designed to pursue high speed and low power consumption. A merged-capacitor technique is implemented in the DAC, while the successive approximations register is based on a single-row architecture with D-FFs. The converter, designed in ST 90nm CMOS technology exhibits a maximum sampling frequency of 1.2 GHz at 1 V supply with a 500 mV input range and 16 mW of power consumption. The simulated figure of merit is 0.3 pJ/conv

A 2.5-V BiCMOS comparator with current-mode interpolation

A high-speed latched comparator based on a current-mode architecture is presented. It achieves a sampling speed of 150 MS/s at 2.5 V supply, with a power consumption lower than conventional schemes. Its very low kickback noise makes it especially suitable for differential analog-to-digital converters (ADCs). Moreover, it supports precise 2X interpolation in current mode at full clock speed, allowing a further reduction of the ADC power consumption. The comparator was implemented in a 0.8 /spl mu/m BiCMOS technology.

Harmonic distortion in high-speed differential A/D converters

The brief discusses the harmonic distortion introduced by the differential input adapter commonly used in flash and folding A/D converters operating without sample and hold. A distributed model of the adapter is proposed, which provides physical insight and allows quantitative evaluation. Moreover, a technique based on a feedforward compensation is presented. It provides a significant reduction of the harmonic distortion with a small increase of the die area.