Alessia Frazzetto

Correlating macroscopic and nanoscale electrical modifications of SiO2/4H-SiC interfaces upon post-oxidation-annealing in N2O and POCl3

This letter reports on the electrical properties of SiO2/4H-SiC interfaces after post-oxidation annealing (POA) in N2O and POCl3. The notably higher channel mobility measured in 4H-SiC MOSFETs subjected to POA in POCl3 was ascribed both to a reduction of the interface traps density and to an increase of donor concentration incorporated in SiC. Scanning spreading resistance microscopy on a SiC surface directly exposed to POA revealed that the incorporation of P-related shallow donors upon POA in POCl3 is more efficient than N-shallow donors incorporation during N2O treatments which subsequently explains the significantly enhanced channel conductivity of the MOSFETs.

Fowler-Nordheim tunneling at SiO2/4H-SiC interfaces in metal-oxide-semiconductor field effect transistors

The conduction mechanisms and trapping effects at SiO2/4H-SiC interfaces in metal-oxide-semiconductor field effect transistors (MOSFETs) were studied by Fowler-Nordheim (FN) tunnelling and frequency dependent conductance measurements. In particular, the analysis of both MOS capacitors and MOSFETs fabricated on the same wafer revealed an anomalous FN behavior on p-type implanted SiC/SiO2 interfaces. The observed FN instability upon subsequent voltage sweeps was correlated to the charge-discharge of hole trap states close the valence band edge of 4H-SiC. The charge-discharge of these traps also explained the recoverable threshold voltage instability observed in lateral MOSFETs.

Influence of the surface morphology on the channel mobility of lateral implanted 4H-SiC(0001) metal-oxide-semiconductor field-effect transistors

The influence of the surface morphology on the channel mobility of 4H-SiC metal-oxide-semiconductor field effect transistors annealed under two different conditions is discussed. The devices were fabricated using post-implantation annealing at 1650 °C. In particular, while the use of a protective capping layer during post-implantation annealing preserved a smooth 4H-SiC surface resulting in a channel mobility of 24 cm2 V−1 s−1, a rougher morphology of the channel region (with the presence of surface macrosteps) was observed in the devices annealed without protection, which in turn exhibited a higher mobility (40 cm2 V−1 s−1). An electrical analysis of SiO2/SiC capacitors demonstrated a reduction of the interface state density from 7.2 × 1011 to 3.6 × 1011 cm−2 eV−1, which is consistent with the observed increase of the mobility. However, high resolution transmission electron microscopy showed an almost atomically perfect SiO2/4H-SiC interface. The electrical results were discussed considering the peculiar...

Near-surface processing on AlGaN/GaN heterostructures: a nanoscale electrical and structural characterization

The effects of near-surface processing on the properties of AlGaN/GaN heterostructures were studied, combining conventional electrical characterization on high-electron mobility transistors (HEMTs), with advanced characterization techniques with nanometer scale resolution, i.e., transmission electron microscopy, atomic force microscopy (AFM) and conductive atomic force microscopy (C-AFM). In particular, a CHF3-based plasma process in the gate region resulted in a shift of the threshold voltage in HEMT devices towards less negative values. Two-dimensional current maps acquired by C-AFM on the sample surface allowed us to monitor the local electrical modifications induced by the plasma fluorine incorporated in the material.The results are compared with a recently introduced gate control processing: the local rapid thermal oxidation process of the AlGaN layer. By this process, a controlled thin oxide layer on surface of AlGaN can be reliably introduced while the resistance of the layer below increase locally.

A look underneath the SiO2/4H-SiC interface after N2O thermal treatments

Summary The electrical compensation effect of the nitrogen incorporation at the SiO2/4H-SiC (p-type) interface after thermal treatments in ambient N2O is investigated employing both scanning spreading resistance microscopy (SSRM) and scanning capacitance microscopy (SCM). SSRM measurements on p-type 4H-SiC areas selectively exposed to N2O at 1150 °C showed an increased resistance compared to the unexposed ones; this indicates the incorporation of electrically active nitrogen-related donors, which compensate the p-type doping in the SiC surface region. Cross-sectional SCM measurements on SiO2/4H-SiC metal/oxide/semiconductor (MOS) devices highlighted different active carrier concentration profiles in the first 10 nm underneath the insulator–substrate interface depending on the SiO2/4H-SiC roughness. The electrically active incorporated nitrogen produces both a compensation of the acceptors in the substrate and a reduction of the interface state density (D it). This result can be correlated with the 4H-SiC surface configuration. In particular, lower D it values were obtained for a SiO2/SiC interface on faceted SiC than on planar SiC. These effects were explained in terms of the different surface configuration in faceted SiC that enables the simultaneous exposition at the interface of atomic planes with different orientations.

Nanoscale electro-structural characterisation of ohmic contacts formed on p-type implanted 4H-SiC

This work reports a nanoscale electro-structural characterisation of Ti/Al ohmic contacts formed on p-type Al-implanted silicon carbide (4H-SiC). The morphological and the electrical properties of the Al-implanted layer, annealed at 1700°C with or without a protective capping layer, and of the ohmic contacts were studied using atomic force microscopy [AFM], transmission line model measurements and local current measurements performed with conductive AFM.The characteristics of the contacts were significantly affected by the roughness of the underlying SiC. In particular, the surface roughness of the Al-implanted SiC regions annealed at 1700°C could be strongly reduced using a protective carbon capping layer during annealing. This latter resulted in an improved surface morphology and specific contact resistance of the Ti/Al ohmic contacts formed on these regions. The microstructure of the contacts was monitored by X-ray diffraction analysis and a cross-sectional transmission electron microscopy, and correlated with the electrical results.

Industrial Approach for Next Generation of Power Devices Based on 4H-SiC

Silicon Carbide metal-oxide-semiconductor field effect transistor (4H-SiC MOSFET) can be considered as the next revolution in power electronics applications. However, a wide market introduction of 4H-SiC MOSFET requires a special focus on device reliability and simplicity of use to replace Silicon switches in existing applications. This paper describes STMicroelectronics (STM) approach to define methodology and design solutions able to guarantee the end-users and to drive their choice toward 4H-SiC MOSFET as an ideal power component.

Comparative Study of the Current Transport Mechanisms in Ni2Si Ohmic Contacts on n- and p-Type Implanted 4H-SiC

The knowledge of the temperature behavior of Ohmic contacts is an important issue to understand the device operation. This work reports an electrical characterization as a function of the temperature carried out on nickel silicide (Ni2Si) Ohmic contacts, used both for n-type and p-type implanted 4H-SiC layers. The temperature dependence of the specific contact resistance suggested that a thermionic field emission mechanism dominates the current transport for contacts on p-type material, whereas a current transport by tunneling is likely occurring in the contacts on n-type implanted SiC. Furthermore, from the temperature dependence of the electrical characteristics, the activation energies for Al and P dopants were determined, resulting of 145 meV and 35 meV, respectively. The thermal stability of the electrical parameters has been demonstrated upon a long-term (up to ~100 hours) cycling in the temperature range 200-400°C.

Characterization of SiO2/SiC Interfaces Annealed in N2O or POCl3

This paper reports a comparative characterization of SiO2/SiC interfaces subjected to post-oxide-deposition annealing in N2O or POCl3. Annealing process of the gate oxide in POCl3 allowed to achieve a notable increase of the MOSFET channel mobility (up to 108 cm2V-1s-1) with respect to the N2O annealing (about 20 cm2V-1s-1), accompanied by a different temperature behaviour of the electrical parameters in the two cases. Structural and compositional analyses revealed a different surface morphology of the oxide treated in POCl3, as a consequence of the strong incorporation of phosphorous inside the SiO2 matrix during annealing. This latter explained the instability of the electrical behaviour of MOS capacitors annealed in POCl3.

Conduction Mechanisms at SiO2/4H-SiC Interfaces in MOS-Based Devices Subjected to Post Deposition Annealing in N2O

This paper reports on the conduction mechanisms through the gate oxide and trapping effects at SiO2/4H-SiC interfaces in MOS-based devices subjected to post deposition annealing in N2O. The phenomena were studied by temperature dependent current–voltage measurements. The analysis of both n and p-MOS capacitors and of n-channel MOSFETs operating in the “gate-controlled-diode” configuration revealed an anomalous hole conduction behaviour through the SiO2/4H-SiC interface, with the onset of current conduction moving towards more negative values during subsequent voltage sweeps. The observed gate current instabilities upon subsequent voltage sweeps were deeply investigated by temperature dependent cyclic gate current measurements. The results were explained by the charge-discharge mechanism of hole traps in the oxide.