Alex Chow

A package demonstration with solder free compliant flexible interconnects

Flexible, stress-engineered spring interconnects are a novel technology potentially enabling room temperature assembly approaches to building highly integrated and multi-chip modules (MCMs). Such interconnects are an essential solder-free technology facilitating the MCM package diagnostics and rework. Previously, we demonstrated the performance, functionality, and reliability of compliant micro-spring interconnects under temperature cycling, humidity bias and high-current soak. Currently, we demonstrate for the first time the package with the 1st level conventional fine pitch C4 solder bump interconnects replaced by the arrays of microsprings. Dedicated CMOS integrated circuits (ICs) have been assembled onto substrates using these integrated microsprings. Metrology modules on the ICs are designed and used to characterize the connectivity and resistance of each microspring site.

Package demonstration of an interposer with integrated TSVs and flexible compliant interconnects

We report on the development of a test package that utilizes a passive silicon interposer with high density and high aspect ratio TSVs, each integrated with compliant flexible interconnect on one side of the interposer. As opposed to conventional approaches, where TSV interposers are populated with C4 and/or fine pitch micro bumps with multiple interfaces to reflow and permanently attach, our TSV interposers are integrated with micro-spring interconnects on a single side or, potentially, on both sides to provide a truly reworkable or reusable (“rematable”) MCM platform. This makes it possible to test die in package while retaining the ability to replace any that are found flawed. This is a key requirement for increasing assembly yield of advanced MCM packages.

Integrating through-silicon vias with solder free, compliant interconnects for novel, large area interposers

A novel packaging module is described that is based on co-integration of flexible micro-spring interconnects with through silicon copper vias (TSVs) into a passive large area silicon interposer. We report on the packaging test vehicles based on such interposers that are designed to demonstrate a wafer scale integration process to form TSV+spring interconnects with high yield and low resistance. Our goal is to develop a scalable, large area die or MCM packaging platform to enable stress-free, readily reworkable packaging of chips and components with different functionality and technology. We show interposer layouts, share process details and characterization methods.

System considerations for wireless capacitive chip-to-chip signaling

Using capacitive-based chip-to-chip signaling in large-scale systems offers an interesting tradeoff between design and packaging complexity versus power consumption and performance. Placing chips together in close proximity offers low energy-per-bit costs and high I/O density, and therefore enables off-chip bandwidth levels far beyond those offered by traditional packaging and I/O technologies. Much of the previous published work on capacitive Proximity I/O has focused on mechanical methods for accurate chip alignment. In this paper we discuss some system design considerations unique to Proximity I/O. First, we compare and contrast circuit and layout techniques that optimize signal-to-noise ratio under expected chip misalignments. Next, we evaluate methods for establishing appropriate DC bias levels across a chip-to-chip capacitive link. Finally, we show a full Proximity I/O implementation to enumerate the required system overheads for clocking and misalignment compensation, and discuss how current trends in memory bandwidth and density are driving large-scale systems towards such solutions.

Current crowding study of a micro spring contact for flip chip packaging

Current crowding of a micro spring pressure contact under high current is studied. The spring conducts > 250 mA electrical current between chips, has large mechanical compliance (> 30 µm) compared to other packaging technologies, and fits in a 180 µm pitch 2d array. At 250 mA and 65 °C, daisy chains of 134 spring contacts in a silicon package show stable resistances and hot spot temperature rises of less than a degree. At 1 A, failure near the spring tip or body is observed. Finite element modeling is performed to study the current density distribution and provide failure spot insight. A strategy is proposed to avoid current crowding.

Employing coherent detection for on-chip six-axis position sensors

Recent interest in multi-chip integration has motivated the development of on-chip sensors to address alignment challenges of assembling complex multi-chip packages. Earlier sensor implementations were susceptible to transistor leakage currents. More recent demonstrations correct this issue by measuring differences in coupling capacitances and using coherent detection to lower the noise floor. In this paper, we discuss these mechanisms that improve the accuracy of on-chip position sensors. We also present new methods of determining chip separation that can leverage coherent detection by measuring only differences in coupling.