Alex Doboli

Scheduling of conditional process graphs for the synthesis of embedded systems

We present an approach to process scheduling based on an abstract graph representation which captures both dataflow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

High-level synthesis of /spl Delta//spl Sigma/ Modulator topologies optimized for complexity, sensitivity, and power consumption

This paper proposes a novel topology-synthesis methodology for single-loop single-bit /spl Delta//spl Sigma/ modulators. The goal is to explore all possible topologies and to obtain the optimal topology under various design considerations, such as hardware complexity, modulator sensitivity, and power consumption. A generic modulator architecture that incorporates all possible feedback and feedforward signal paths was defined and the symbolic noise transfer function (NTF) and signal transfer function (STF) for the generic topology were derived. The symbolic functions were then used to formulate the topology-exploration problem as a mixed-integer nonlinearly constrained programming (MINLP) problem that simultaneously generates and selects the optimal modulator topology with respect to the cost function. Experiments show the superiority of synthesized topologies as compared to traditional modulator topologies.

Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS

High-level synthesis is highly demanded for managing the complexity of analog and mixed-signal system designs. However, synthesis methods are currently in their infancy. The absence of a high-level specification notation is an important limitation for the development of efficient synthesis methods. This paper presents a behavioral model and a VHDL-AMS subset for high-level synthesis of analog and mixed-signal systems. The model (named aBlox) offers a composition semantics for functionality description and an orthogonal declarative mechanism for expressing the performance requirements of a system. The model was developed after analyzing a large number of systems for telecommunication, signal processing, control engineering, and analog computing. The model expresses the meaning of: 1) analog and digital data; 2) continuous and event-driven functionality (behavior); 3) analog performance attributes; and 4) analog-digital interactions. The aBlox model serves as a foundation for defining a semantically sound VHDL-AMS subset for synthesis. Also, the VHDL-AMS subset is identified so that its constructs can be mapped to architectures of circuits. We introduce several restrictions to the VHDL-AMS instructions, such that their semantics match that of the aBlox model. To motivate the usefulness of the model and the VHDL-AMS subset, we present a case study that uses VHDL-AMS inputs.

Behavioral synthesis of analog systems using two-layered design space exploration

This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. The synthesis process produces a netlist of electronic components that are selected from a component library and sized such that the overall area is minimized and the rest of the performance constraints such as power, slew-rate, bandwidth, etc. are met. The gap between system level specifications and implementations is bridged using a hierarchically-organized, design-space exploration methodology. Our methodology performs a two-layered synthesis, the first being architecture generation, and the other component synthesis and constraint transformation. For architecture generation we suggest a branch-and-bound algorithm, while component synthesis and constraint transformation use a genetic algorithm based heuristic method. Crucial to the success of our exploration methodology is a fast and accurate performance estimation engine that embeds technology process parameters, SPICE models for basic circuits and performance composition equations. We present a telecommunication application as an example to illustrate our synthesis methodology, and show that constraint-satisfying designs can be synthesized in a short time and with a reduced designer effort.

Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies

This paper presents a methodology for high-level synthesis of continuous-time linear analog systems. Synthesis results are architectures of op-amps, sized resistors and capacitors such that their ac behavior and total silicon area are optimized. Bounds for op-amp dc gain, unity-gain frequency, input, and output impedances are found as a byproduct of synthesis. Subsequently, a circuit synthesis tool can be used to synthesize the op-amps of an architecture. The paper details the architecture generation technique. Architecture generation produces alternative architectures for a system specification using the tabu search heuristic. Its main advantages over traditional methods is that it is application independent, does not require a library of block connection patterns, and is simple to implement. The paper also discusses the hierarchical, two-step parameter optimization that guides architecture generation. Experiments showed that linear analog systems operating at low/medium frequencies (like telecommunication systems and filters) can be synthesized in a reasonably long time and with reduced effort.

Layout conscious bus architecture synthesis for deep submicron systems on chip

System-level design has a disadvantage in not knowing important aspects about the final layout. This is critical for SoC, where uncertainties in communication delay by very deep submicron effects cannot be neglected. This paper presents a layout-aware bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. BA synthesis includes finding bus topology and routing individual buses, so that constraints like area, bus speed and length, are tackled at the physical level. The paper presents the BA automatically synthesized for a network processor and a JPEG SoC.

A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications

This paper presents a synthesis methodology for analog systems described using VHDL-AMS language. Synthesis produces net-lists of analog components that are selected from a library, and sized so that specified objectives (like AC response, signal to noise ratio, dynamic range, area) are optimized. The gap between abstract specifications and implementations is bridged using a two-layered methodology. The first layer is architecture generation. The second layer is component synthesis and constraint transformation. Architecture generation employs the branch-and-bound algorithm to create architectural alternatives for a system. Component synthesis and constraint transformation use a directed interval based genetic algorithm that operates on parameter ranges. The performance estimation engine embeds technology process parameters, SPICE models for basic circuits, and symbolic composition equations for basic structural configurations. The paper discusses the VHDL-AMS subset for synthesis. The subset offers the composition semantics. As a result, specifications offer sufficient insight into the system structure to allow automated architecture generation. To justify the flexibility of the methodology, the paper presents results for three case studies, a signal conditioning system, a filter, and an analog to digital converter. Experiments show that constraint-satisfying designs can be synthesized in a short time, at a low cost, and without requesting broad knowledge on analog circuits.

Systematic development of analog circuit structural macromodels through behavioral model decoupling

This paper presents a systematic methodology to create customized structural macromodels for a specific analog circuit. The novel contributions of the method include definition of the building block behavioral concept and two original algorithms to generate structural models. Experiments are offered for two-stage opamp and operational transconductance amplifier (OTA) circuits. The automatically produced models are accurate, offer design insight, and require low modeling effort.

TUKI: A voice-activated information browser

The purpose of the presented system is to recognize the users voice which is then converted into system recognizable commands. The system connects to the Internet and uses the commands to navigate through the Internet. In doing so, it reads back news from various websites to the user through a speaker. The system is designed to use natural language processing, meaning the user is able to converse with the system as if they were talking to an actual person.

A VHDL-AMS compiler and architecture generator for behavioral synthesis of analog systems

This paper presents a complete method for automatically translating VHDL-AMS behavioral-specifications of analog systems into op amp level net-lists of library components. We discuss the three fundamental aspects, that pertain to any behavioral synthesis environment the specification language, the rules for compiling language constructs into a technology-independent, intermediate representation, and the synthesis (mapping) of representations to net-lists (topologies) of library components, so that performance constraints are satisfied. We motivate the effectiveness of the method by presenting our synthesis results for 5 examples.