Nattawut Thepayasuwan

Layout conscious bus architecture synthesis for deep submicron systems on chip

System-level design has a disadvantage in not knowing important aspects about the final layout. This is critical for SoC, where uncertainties in communication delay by very deep submicron effects cannot be neglected. This paper presents a layout-aware bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. BA synthesis includes finding bus topology and routing individual buses, so that constraints like area, bus speed and length, are tackled at the physical level. The paper presents the BA automatically synthesized for a network processor and a JPEG SoC.

Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed

This paper presents a layout-conscious approach for hardware/software codesign of systems-on-chip (SoCs) optimized for latency, including an original algorithm for bus architecture synthesis. Compared to similar work, the method addresses layout related issues that affect system optimization, such as the dependency of task communication speed on interconnect parasitic. The codesign flow executes three consecutive steps: 1) combined partitioning and scheduling: besides partitioning and scheduling, this step also identifies the minimum speed constraints for each data link; 2) IP core placement, bus architecture synthesis, and routing: IP cores are placed using a hierarchical cluster growth algorithm; bus architecture synthesis identifies a set of possible building blocks and then assembles them for minimizing bus length and complexity; poor solutions are pruned using a special table structure and select-eliminated method; and 3) rescheduling for the best bus architecture. This paper offers extensive experiments for the proposed codesign method, including bus architecture synthesis for a network processor and a JPEG SoC.

Bus architecture synthesis for hardware-software co-design of deep submicron systems on chip

System level design always has a disadvantage of not possessing detailed knowledge of the communication subsystem. This is a crucial issue for system-on-chip design, where uncertainty in communication by very deep submicron effects cannot be neglected. We present a bus architecture (BA) synthesis algorithm for designing the communication subsystem of an SoC. The algorithm is part of a hardware-software codesign methodology for resource constrained embedded applications. BA synthesis includes finding the bus topology, and routing the individual buses so that various constraints, like bus length, topology complexity, potential for communication conflicts over time, are addressed. We present BA synthesis results for a network processor, and a JPEG SoC.

Hardware-software co-design of resource constrained systems on a chip

We present a hardware-software codesign methodology for resource constrained SoC fabricated in a deep submicron process. The novelty of the methodology consists in contemplating critical hardware and layout aspects during system level design for latency optimization. The effect of interconnect parasitic and delays is considered for characterizing bus speed and data communication times. The methodology permits coarse and medium grained resource sharing across tasks for execution speedup through superior usage of hardware. We offer experiments for the proposed codesign methodology, including a JPEG SoC.

OSIRIS: automated synthesis of flat and hierarchical bus architectures for deep submicron systems on chip

This paper presents a bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. The novelty is that a potential variable at physical level, namely, total bus length is contemplated during the synthesis process. The algorithm generates both flat and hierarchical bus architecture using performance parameters, i.e., bus length, topology complexity, potential for communication conflicts over time. BA synthesis results for a network processor are discussed.

A continuous time markov decision process based on-chip buffer allocation methodology

We have presented an optimal on-chip buffer allocation and buffer insertion methodology which uses stochastic models of the architecture. This methodology uses finite buffer space and presents a method to distribute this finite space in an optimal fashion. Such a methodology is useful in managing the scarce buffer resources available on chip as compared to network based data communication which can have large buffer space. The methodology also uses Continuous Time Markov Decision Processes CTMDPs. The modeling of this problem in terms of a CTMDP framework lead to a nonlinear formulation due to usage of bridges in the bus architecture. We present a methodology to split the problem into several smaller, though linear systems and we then solve these subsystems.

Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policies

Design and analysis of communication subsystems is a crucial issue for system-on-chip design, where uncertainty in communication by very deep sub micron effects cannot be neglected. This paper presents a bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. The methodology combines both BA space exploration as well as generation analysis of arbitration policies to guarantee a feasible solution at transaction level where optimized policy is assigned. BA synthesis includes finding the bus topology, and routing the individual buses so that various constraints, like bus length, topology complexity, potential for communication conflicts over time, are addressed. Heuristic arbitration policies as well as Markov decision process (MDP) based policies have been simulated over a queueing model of the architecture and compared with respect to performance metrics like queue length, time spent in buffer and power consumption. The paper presents BA synthesis results for a network processor.

An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications

The design of mixed analog-digital systems requires new CAD tools, as specific performance requirements need to be tackled i.e. simultaneous switching noise (SSN). This paper proposes a novel technique for resource binding and operation scheduling. The goal is to maximize the latency of the digital hardware such that its SSN is kept within feasible limits. The technique includes two steps: (1) for each input specifications, Performance Models (PM) are automatically generated for the overall throughput and SSN values, and (2) PMs are employed by an exploration algorithm to find the best resource binding and operation scheduling alternative. Experiments showed the ability of the proposed technique to find good solutions as compared to traditional high-level synthesis methods.