Alexander Grekov

A Physics-Based Model for a SiC JFET Accounting for Electric-Field-Dependent Mobility

In this paper, a physical model for a SiC Junction Field Effect Transistor (JFET) is presented. The novel feature of the model is that the mobility dependence on both temperature and electric field is taken into account. This is particularly important for high-current power devices where the maximum conduction current is limited by drift velocity saturation in the channel. The model equations are described in detail, emphasizing the differences introduced by the field-dependent mobility model. The model is then implemented in Pspice. Both static and dynamic simulation results are given. The results are validated with experimental results under static conditions and under resistive and inductive switching conditions.

Power SiC DMOSFET Model Accounting for Nonuniform Current Distribution in JFET Region

The main goal of this paper is development of a new circuit-based silicon carbide (SiC) DMOSFET model which physically represents the mechanism of current saturation in power SiC DMOSFET. Finite-element simulations show that current saturation for a typical device geometry is due to 2-D carrier distribution effects in the JFET region caused by current spreading from the channel to the JFET region. For high drain-source voltages, most of the voltage drop occurs in the current spreading region located in the JFET region close to the channel. A new model is proposed that represents the nonuniform current distribution in the JFET region using a nonlinear voltage source and a resistance network. Advantages of the proposed model are that a single set of equations describes operation in both the linear and saturation regions, and that it provides a more physical description of MOSFET operation.

Parasitic modeling for accurate inductive switching simulation of converters using SiC devices

In this paper, the parasitic inductances for inductive switching of SiC devices in a switching converter were modeled and analyzed using a 3-D inductance extraction program. A double pulse test-bench was built to characterize the resistive and inductive switching behavior of the SiC devices. In order to capture the parasitic ringing in the fast switching transient, the gate-to-source switching loop and drain-to-source switching loop parasitic inductances of the PCB layout are extracted by the 3D inductance extraction program. The system model in Pspice includes SiC device models and the extracted parasitic elements. Simulation results are compared with experimental results. The comparison shows good agreement between simulation and experimental results under both resistive and inductive switching conditions.

Effect of crystallographic defects on the reverse performance of 4H–SiC JBS diodes

Abstract A quantitative analysis of the effect of crystallographic defects on the performance of 4H–SiC junction barrier Schottky (JBS) diodes was performed. It has been shown that higher leakage current in diodes is associated with a greater number of elementary screw dislocations. Further, threading dislocation pair arrays were observed in some of the fabricated devices and, for the first time, the role of such defects on JBS reverse leakage currents is investigated.

Parameter Extraction Procedure for a Physics-Based Power SiC Schottky Diode Model

A detailed parameter extraction procedure for a simple physics-based power silicon carbide (SiC) Schottky diode model is presented. The developed procedure includes the extraction of carrier concentration, active area, and thickness of the drift region, which are needed in the power Schottky diode model. The main advantage is that the developed procedure does not require any knowledge of device fabrication, which is usually not available to circuit designers. The only measurements required for the parameter extraction are simple static I-V characterization and C-V measurements. Furthermore, the physics-based SiC Schottky diode model whose parameters are extracted by the proposed procedure includes temperature dependences and is generally applicable to SiC Schottky diodes. The procedure is demonstrated for five Schottky diodes from two different manufacturers having the following ratings: 600 V/50 A, 1.2 kV/3 A, 1.2 kV/7 A, 1.2 kV/20 A, and 600 V/4 A.

Parameter Extraction Procedure for Vertical SiC Power JFET

A practical parameter extraction procedure for a power silicon carbide (SiC) junction field-effect transistor (JFET) is presented. The carrier mobility and carrier concentration are very important parameters, strongly affecting the device current capability and dynamic characteristics for a given design. When modeling JFETs, the values of these parameters are usually based on assumptions and given by a vendor in a range. As a result, model accuracy is compromised. In this paper, a step-by-step parameter extraction procedure is described that includes the extraction of mobility and carrier concentration in the channel and drift regions based on knowledge of device geometrical parameters. For the first time, carrier mobilities in the channel and drift regions of a power JFET are extracted individually. It is found that channel and drift region mobilities can be very different for a given device since they are strongly dependent on the fabrication process. The separate extraction of these two mobilities can also improve model accuracy in the case of imperfect knowledge of the device geometry. The developed procedure includes the extraction of empirical parameters describing the temperature dependence of mobilities in the channel and drift regions. A simple static I- V characterization and C-V measurements are the only measurements required for the parameter extraction. In this paper, the procedure is experimentally validated for both normally off (enhancement mode) and normally on (depletion mode) JFETs.

Forward voltage drop degradation in diffused SiC p-i-n diodes

The time varying relationship between forward voltage drop and temperature in degrading diffused 4H–SiC p-i-n diodes was used to estimate the activation energy (0.34 eV) of the degradation process associated with the formation of stacking faults (SFs). A very strong peak appeared in the electroluminescence spectra at 427 nm and increased steadily in intensity as the forward voltage drop increased. The mismatch stresses, localized in the diffused doped region, are proposed to play a dominant role in the initial formation of SFs. Calculations were performed for the phonon pressure caused by nonradiative carrier recombination, which presumably is responsible for the development and motion of the SFs leading to the observed forward voltage degradation.

Vertical SiC JFET model with unified description of linear and saturation operating regions

A novel SiC junction field effect transistor (JFET) model is proposed that uses a unified description of linear and saturated conduction modes. Advantages of the proposed model are improved robustness and convergence, inclusion of fielddependent mobility effects, and more physical description of the current saturation phenomenon. The model is validated against a normally-off JFET sample over a wide temperature range. Finite element simulation are used to demonstrate the physicsbased nature of the proposed model.

Parameter extraction procedure for high power SiC JFET

A practical parameter extraction procedure for power junction field effect transistor (JFET) is presented. The carrier mobility and carrier concentrations are very important parameters, strongly affecting the current capability and dynamic characteristics of the device for a given design. When modeling JFETs, values of these parameters usually are based on assumptions and given by a vendor in a range. As a result, model accuracy is compromised. In this paper, a step-by-step parameter extraction procedure is described that includes extraction of the mobility and the carrier concentration in the channel and drift regions based on knowledge of the device geometrical parameters. For the first time, carrier mobility in channel and drift regions of power JFET are extracted individually. It is found that channel and drift region mobilities can be very different for a given device, since they are strongly fabrication-process dependent. The developed procedure includes extraction of parameters for proposed empirical temperature dependencies of mobilities in the channel and drift regions. A simple static I-V characterization and C-V measurements are the only measurements required for the parameter extraction.

Parameter extraction procedure for a physics-based power SiC Schottky diode model

A detailed parameter extraction procedure for a simple physics-based power SiC Schottky diode model is presented. The developed procedure includes the extraction of doping concentration, active area and thickness of drift region, which are needed in the power Schottky diode model. The main advantage is that the developed procedure does not require any knowledge of device fabrication, which is usually not available to circuit designers. The only measurements required for the parameter extraction are a simple static I-V characterization and C-V measurements. Furthermore, the physics-based SiC Schottky diode model whose parameters are extracted by the proposed procedure includes temperature dependencies and is generally applicable to SiC Schottky diodes. The procedure is demonstrated for four Schottky diodes from two different manufacturers having the following ratings: 600V/50A, 1.2kV/3A, 1.2kV/7A, and 1.2kV/20A.