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Dive into the research topics where Alexander J. Suess is active.

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Featured researches published by Alexander J. Suess.


international conference on computer aided design | 1995

Timing analysis with known false sub graphs

Krishna P. Belkhale; Alexander J. Suess

In this paper we formulate the problem of timing analysis with known false sub graphs. This problem is important when we want the timing analysis system to take into account false path information that is supplied either by the user or by another program, and supply accurate timing information to optimization programs such as placement and wiring. We present an efficient algorithm for the problem.


Archive | 2003

System and method for correlated process pessimism removal for static timing analysis

Kerim Kalafala; Peihua Qi; David J. Hathaway; Alexander J. Suess; Chandramouli Visweswariah


Archive | 1999

Method for handling coupling effects in static timing analysis

David J. Hathaway; Chandramouli V. Kashyap; Byron Krauter; Sharad Mehrotra; Alexander J. Suess


Archive | 2006

Method for fast incremental calculation of an impact of coupled noise on timing

Gregory M. Schaeffer; Alexander J. Suess; David J. Hathaway


Archive | 2007

Method, computer program product, and apparatus for static timing with run-time reduction

James C. Gregerson; Kerim Kalafala; Alexander J. Suess


Archive | 2007

Method for generating a skew schedule for a clock distribution network containing gating elements

Revanta Banerji; David J. Hathaway; Alex Rubin; Alexander J. Suess


Archive | 2010

Method for enabling multiple incompatible or costly timing environment for efficient timing closure

Frank J. Musante; William E. Dougherty; Nathaniel D. Hieter; Alexander J. Suess


Archive | 2015

INTEGRATION OF FUNCTIONAL ANALYSIS AND COMMON PATH PESSIMISM REMOVAL IN STATIC TIMING ANALYSIS

Peter C. Elmendorf; Kerim Kalafala; Stephen G. Shuma; Alexander J. Suess


Archive | 2014

Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit

Bijian Chen; David J. Hathaway; Nathaniel D. Hieter; Kerim Kalafala; Jeffrey S. Piaget; Alexander J. Suess


Archive | 2006

PROCESS AND APPARATUS FOR ESTIMATING CIRCUIT DELAY

Harry J. Beatty; David J. Hathaway; Alexander J. Suess

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