David J. Hathaway

EDA in IBM: past, present, and future

Throughout its history, from the early four-circuit gate-array chips of the late 1960s to todays billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBMs contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

Compact modeling of variational waveforms

In ultra-deep sub-micron technologies, modeling waveform shapes correctly is essential for accurate timing and noise analysis. Due to process and environmental variations, there is a need for a variational waveform model that is compact, efficient and accurate. The mode) should capture correlations due to common dependence on process parameters. This paper proposes a waveform model derived from basic transformations of a nominal waveform in the absence of variations. The transformations are parameterized by variational quantities that capture the sensitivity of the waveform to process parameters. The resulting waveform model works well with current-source models for static timing analysis. Numerical results are presented to demonstrate the accuracy of the model both in capturing variational waveforms and in propagating waveforms through logic gates.

Quality of EDA CAD tools: definitions, metrics and directions

In this paper we survey major problems faced by EDA tools in tackling deep submicron (DSM) design challenges like: crosstalk, reliability, power and interconnect dominated delay. We discuss the need for rethinking quality models used in EDA tools to allow early and reliable planning, estimation, analysis, and optimization. Key design quality metrics from a CAD tool perspective are surveyed, and methodologies and directions are proposed for the next generation design automation tools, intended to meet the challenges ahead. Ideas such as forward synthesis, incremental synthesis, system-level interconnect prediction and planning, and their implications on design quality design tool architecture, and design methodology are explored.

Circuit placement chip optimization, and wire routing for IBM IC technology

Recent advances in integrated circuit technology have imposed new requirements on the chip physical design process. At the same time that performance requirements are increasing, the effects of wiring on delay are becoming more significant. Larger chips are also increasing the chip wiring demand, and the ability to efficiently process these large chips in reasonable time and space requires new capabilities from the physical design tools. Circuit placement is done using algorithms which have been used within IBM for many years, with enhancements as required to support additional technologies and larger data volumes. To meet timing requirements, placement may be run iteratively using successively refined timing-derived constraints. Chip optimization tools are used to physically optimize the clock trees and scan connections, both to improve clock skew and to improve wirability. These tools interchange sinks of equivalent nets, move and create parallel copies of clock buffers, add load circuits to balance c lock net loads, and generate balanced clock tree routes. Routing is done using a grid-based, technology-independent router that has been used over the years to wire chips. There are numerous user controls for specifying router behavior in particular areas and on particular interconnection levels, as well as adjacency restrictions.

Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis

We introduce a generalized, efficient, and accurate power abstraction model and generation techniques for complex IP blocks. This is based on the contributor based power modeling concept, which exploits the nature of power consuming components in a design being inherently separable. The generated power abstraction is Process, Voltage and Temperature (PVT) independent, thus enabling very efficient hierarchical power analysis. Our approach constitutes the industrys first design methodology to automatically generate PVT independent contributor based abstracts. We also describe extensions to the power contributor concept to model dynamic power. Extensive analysis and results on real industry designs to study the accuracy impacts of abstraction as a function of design types and sizes are presented. We also present model to hardware correlation experiments demonstrating the application of this abstraction based methodology on the IBM Power7+ server microprocessor chip.

A 300 K-circuit ASIC logic family CAD system

A computer-aided design (CAD) system has been developed to design CMOS application-specific integrated circuit (ASIC) logic family chips denser than any previously available, with performance comparable to bipolar technology. Design flow and key new features are described, and test chip results are given. Logic synthesis and transformation systems translate the designs to a technology-independent internal representation; optimize them for area, performance, and testability; and translate them to an implementation in the technology circuit library. The synthesis systems add logic circuits needed for testing and generate information about the clock trees used later in physical clock-free construction.<<ETX>>

Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology

Recent advances in integrated circuit technology have imposed new requirements on the chip physical design process. At the same time that performance requirements are increasing, the effects of wiring on delay are becoming more significant. Larger chips are also increasing the chip wiring demand, and the ability to efficiently process these large chips in reasonable time and space requires new capabilities from the physical design tools. Circuit placement is done using algorithms which have been used within IBM for many years, with enhancements as required to support additional technologies and larger data volumes. To meet timing requirements, placement may be run iteratively using successively refined timing-derived constraints. Chip optimization tools are used to physically optimize the clock trees and scan connections, both to improve clock skew and to improve wirability. These tools interchange sinks of equivalent nets, move and create parallel copies of clock buffers, add load circuits to balance clock net loads, and generate balanced clock tree routes. Routing is done using a grid-based, technology-independent router that has been used over the years to wire chips. There are numerous user controls for specifying router behavior in particular areas and on particular interconnection levels, as well as adjacency restrictions.

A comprehensive CAD system for high-performance 300 K-circuit ASIC logic chips

A computer-aided design (CAD) system has been developed to support design of CMOS application-specific integrated circuit (ASIC) logic chips containing more than 300 K equivalent two-input NANDs with 180-ps typical gate delays. The underlying technology is a 0.8- mu m, four-level-metal, single-poly CMOS process, with a 0.45- mu m nominal effective channel length and 180-ps typical gate delay. Both standard-cell and gate-array circuit libraries are provided, including fixed and growable memory macros. Key new system features are described in the areas of high-level design and synthesis, delay calculation and timing analysis, timing guidance to physical design, physical design, clock construction, and test generation. Early processing results are reported for several test chips, including a 9.7-mm 2-million-transistor chip and a 14.5-mm 300 K-equivalent-gate chip. >

A reduced circuit library design system

A reduced circuit library using triple-level metal CMOS consisting of nine primitive logic circuits and five latch kernels is proposed for a gate array library. A grouping program has been written to combine these circuits automatically into complex functions which are then hierarchically placed and wired to achieve the density and performance of a more complex library. This approach provides a set of complex functions which is optimized for each specific application while reducing the resource needed for library development and maintenance.<<ETX>>