Alexander Klimm

A system architecture for reconfigurable trusted platforms

For improving the security of embedded systems, trusted computing is a promising technology. For the area of microprocessors in general and personal computers in particular the Trusted Computing Group (TCG) has published detailed specifications. The resulting hardware has been available for some years. This contribution discusses the feasibility of deploying ideas from trusted computing in the domain of reconfigurable hardware, esp. FPGAs, and possible benefits and drawbacks. We give a proposal to use actually available FPGA technology to build a trusted platform on reconfigurable hardware. We also show how trusted computing can deal with partial dynamic reconfiguration while still allowing the user to fully exploit its potentials.

An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores

In embedded systems, especially in multi-purpose platforms, the need for computational power can vary greatly. This depends mainly on the type of applications running on the platform as well as on limitations such as real-time constraints or the amount of data being processed. These factors can change during lifetime of the system and even during runtime. A highly adaptive computing platform is desirable, providing exactly the computational power and speed needed for any particular task at any particular time using minimal resources. This contribution discusses a highly scalable multiprocessor system composed of minimal sized processor cores. The proposed architecture is intended for computational intensive applications such as on-line routing and placement on FPGAs or applications in the cryptographic domain. While offering a lot of leeway in computational power it uses minimal resources on an FPGA, thus freeing hardware resources for applications running in parallel to the multiprocessor system.

A Prototype of Trusted Platform Functionality on Reconfigurable Hardware for Bitstream Updates

Abstract This contribution proposes a secure and efficient method for updating reconfigurable hardware devices like FPGAs by using trusted computing technology. An interesting application is latent in the domain of embedded systems like in the automotive sector when durable products shall be updated in the field while stringent safety and security constraints have to be met. We propose an architecture to send arbitrary FPGA configuration bitstreams personalized to specific platforms over public channels. By using trusted platform modules we achieve a secure delivery chain for IP cores without the need of predefined shared secrets or keys. Furthermore integrity and confidentiality of the IP and enforcement of usage policies can be guaranteed. This enables the vendor to ensure a correct configuration of the device in order to adhere safety commitments. As a side effect such methods can also be used to deliver IP-cores from multiple IP vendors to remote devices securely and efficiently.

A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs

A Hardware/Software Codesign approach based on a MicroBlaze softcore processor and a GF2n-coprocessor module to form a minimal hardware architecture for HECC on low-cost Xilinx FPGAs is described in this paper. Exploiting the features of the MicroBlazes integrated interfaces instructions are streamed on-demand to the coprocessor to keep the controlflow highly flexible. At the same time the dataflow between hardware and software is minimized. Comparison with previous architectures shows high acceleration of HECC with minor increase in hardware resources. It is demonstrated that this speed-up can be used for countermeasures on algorithmic level against basic side-channel attacks while still keeping real-time constraints.

A hardware/software codesign of a co-processor for real-time hyperelliptic curve cryptography on a Spartan3 FPGA

This paper describes the acceleration of calculations for public-key cryptography on hyperelliptic curves on very small FPGAs. This is achieved by using a Hardware/Software Codesign Approach starting with an all-software implementation on an embedded Microprocessor and migrating very time-consuming calculations from software to hardware. Basic GF(2n)-hardware extensions are connected to work in conjunction with the Microprocessor and possible alternatives for connecting external hardware to the Microprocessor are investigated. The performance of the hardware implementations compared to their counterparts as a software approach are evaluated. Based on these results, a coprocessor is devised and optimized for performance. The system utilizes minimal resources and fits easily on a small FPGA. It allows for fast Hyperelliptic Curve Cryptography (HECC) operations while running at a very low clock speed of 33 MHz, thus making it suitable for usage in embedded systems.

Configuration Measurement for FPGA-based Trusted Platforms

This paper proposes a method for measuring hardwareconfigurations for trusted platforms based on field programmablegate arrays (FPGA). The proposed system setupallows for partial reconfiguration as well as full reconfigurationof FPGA devices that can be used additionallyas trusted platforms. In the system, slots are defined forfast partial dynamic reconfiguration. Predefined IP blocksmay be configured into these. The reconfiguration is monitoredand reported to a trusted platform module (TPM).Important configuration characteristics are extracted fromthe bitstream, stored, and evaluated in terms of predefinedpolicies to ensure the integrity of the trusted FPGA platform.By incorporating this method the chain-of-trust known fromtrusted computing is extended into the underlying hardware.This enables remote verifiers to ensure a correct configurationof the device in order to adhere to safety commitmentsand allows for highly adaptive, trusted system-on-chips.

A flexible integrated cryptoprocessor for authentication protocols based on hyperelliptic curve cryptography

An integrated cryptographic processor for public key cryptography for embedded systems is proposed in this contribution. The architecture is designed for computational intensive applications based on hyperelliptic curve cryptography (HECC) in the automotive domain. Authentication protocols based on HECC can be adapted for access control systems and demobilizer applications in todays cars. They can raise the security level of these systems, but ask for more computation power than is available in current automotive platforms. Good programmability of the system in high level languages such as C eases the integration of the proposed platform into existing systems and development flows in the automotive domain. In order to include such a level of abstraction a software programmable application specific processor was developed. This processor allows to hide the complex hardware of HECC and avoids a long term hardware development in case of a re-design. The benefit of a software based system combined with a specialized hardware is provided with the described approach. The presented work therefore follows the novel methodology of hardware software codesign where the benefits of both development methodologies are combined in the final system. Experiments show that a substantial gain in computation speed can be achieved while keeping the gate count low.

A V2X message evaluation methodology and cross-domain modelling of safety applications in V2X-enabled E/E-architectures

The introduction of Vehicular Ad-Hoc Networks (VANETs) enables great potential for improving road traffic flow and especially active safety applications such as cooperative adaptive cruise control (CACC). Such applications not only rely on continuous broadcast of vehicle state information (beacons) of all vehicles, but also have strict real-time requirements. Regarding automotive E/E architectures this continuous broadcasting adds heavy internal E/E data traffic that needs to be processed in real-time by Electronic Control Units (ECUs). In this work we address this issue by proposing a novel cluster-based message evaluation methodology to significantly reduce internal E/E network traffic by discarding irrelevant messages. The approach is only depending on information received over beacons. It combines a vehicle clustering strategy as well as network and vehicle state monitoring capabilities in order to correctly evaluate messages under real-time constraints. The proposed methodology is modeled inside an abstract ECU. It is evaluated by simulating a model-based CACC application under different traffic scenarios. It is shown that a significant reduction of messages is achievable, while still guaranteeing accident-free behavior of CACC.

The Road to "ITIV Labs" - An Integrated Concept for Project-Oriented Systems Engineering Education

This article proposes an integrated concept of anongoing lab series giving electrical engineering and informationtechnology students practical experiences in system engineering,project-based and team-oriented work. Labs start at the firstsemester with fundamentals based on simultaneously givenlectures for three semesters. On the graduate level an adhesiveintegrated lab concept is offered for a multi-perspective view inthe concept of project-oriented systems engineering.

Hardware Support for Authentication in Cyber Physical Systems

Abstract The efficiency and benefit of Cyber Physical Systems (CPS) depend heavily on interconnection of individual devices or nodes. Exchange of data, information relevant to an overall task or functionality is the key to many applications such as smart grids, smart cities, and many others. Trustworthiness of data is needed to make such systems successful. To be able to fulfill policies to guarantee the safety of all entities within a CPS and to provide security measures to enforce these cryptographic solutions have to be embedded. As we show in this paper it is possible to integrate security building blocks in ultra-small devices to provide essential properties for secure embedded systems. With proper policies, high cryptographic standards, rising acceptance by users, and provable security and safety measures, CPS will open countless possibilities to increase efficiency in many aspects of our everyday lives. Zusammenfassung Die Vorteile und Effizienz von Cyber Physical Systems (CPS) hängen definitionsgemäß stark von der Kommunikation der einzelnen Geräte oder Knoten ab, beispielsweise in den Bereichen Smart Grid oder Smart Cities. Hierbei ist die Vertrauenswürdigkeit der Daten von essentieller Bedeutung. Um dies und die Sicherheit der Knoten innerhalb des Netzes zu gewährleisten, müssen kryptographische Mechanismen in die Knoten eingebettet werden. In diesem Beitrag wird gezeigt, wie Grundbausteine für Security in einfache Geräte integriert und so die Grundlagen für sichere eingebettete Systeme gelegt werden können. Zusammen mit hohen Sicherheitsstandards, steigender Akzeptanz der Nutzer und beweisbaren Sicherheitsmechanismen werden CPS unzählige Möglichkeiten eröffnen, die Effizienz und den Komfort in vielen Bereichen unseres Lebens zu steigern.