Alexander Krupp

UML-B Specification for Proven Embedded Systems Design

1 An Introduction to Formal Methods.- 2 Formally Unified System Specification Environment with UML, B and SystemC.- 3 Embedded System Design Using the PUSSEE Method.- 4 System Level Modelling and Refinement with EventB.- 5 The UML-B Profile for Formal Systems Modelling in UML.- 6 U2B.- 7 BHDL.- 8 Towards a Conceptual Framework for UML to Hardware Description Language Mappings.- 9 Interface-Based Synthesis Refinement in B.- 10 Refinement of Finite State Machines with Complementary Model Checking.- 11 Adaptive Cruise Control Case Study Design Experiment.- 12 Adaptive Cruise Controller Case Study.- 13 Formal Modelling of Electronic Circuits Using Event-B.- 14 The Echo Cancellation Unit Case Study.- 15 Results of the Mobile Design System Experiment.- 16 UML-B Specification and Hardware Implementation of a Hamming Coder/Decoder.- 17 The PUSSEE Method in Practice.- A1 Evaluation Criteria for Embedded System Design Methods.

TestML - A Test Exchange Language for Model-Based Testing of Embedded Software

Test processes in the automotive industry are tool-intensive and affected by technologically heterogeneous test infrastructures. In the industrial practice a product has to pass tests at several levels of abstraction such as Model-in-the-Loop (MIL), Software-in-the-Loop (SIL) and Hardware-in-the-Loop (HIL) tests. Different test systems are applied for this purpose (e.g. dSPACE MTest, dSPACE Automation Desk, National Instruments Teststand) and almost each test system requests its own proprietary test description language. The exchange of tests between different test systems and the reuse of tests between different test levels is normally not possible. Efforts to integrate these heterogeneous test environments, to address test exchange in a general manner and to standardize and harmonize the existing language environment are still at the beginning and not tailored towards the requirements of the automotive domain. To keep the whole development and test process efficient and manageable, the definition of an integrated and seamless approach is required. TestML --- the test exchange language we present in this article --- is defined to overcome the technological obstacles (different test language syntax and semantics, different data formats and interface descriptions) that almost automatically accompany the application of heterogeneous test tools and test infrastructures. TestML supports the exchange of tests between different test notations in a heterogeneous tool environment. In this paper, we introduce the XML schema of TestML and demonstrate the efficiency of the interchange format by giving examples from the model-based development of electronic control units. Tool support is illustrated by an application with Simulink/Stateflow.

An Extension of the Classification-Tree Method for Embedded Systems for the Description of Events

Abstract Nowadays, model-based test approaches are indispensable for the quality assurance of in-vehicle control software. In practice, the Classification-Tree Method for Embedded Systems (CTM EMB ) is used to realize a compact graphical representation of test scenarios. Up to now, the CTM EMB has been used mainly in the area of continuous systems. Though the depiction of events within test scenarios is possible already by using existing means of description, there is still room for improvements. Thus, we will introduce in the following a novel extension of the Classification-Tree Method for Embedded Systems for a compact, natural depiction of event-like behaviour which we will illustrate by means of several examples from the area of in-vehicle control software.

Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems

We introduce a structured methodology for the generation of executable test environments from textual requirement specifications via UML class diagrams and the application of the classification tree methodology for embedded systems. The first phase is a stepwise transformation from unstructured English text into a textual normal form (TNF), which is automatically translated into UML class diagrams. After annotations of the class diagrams and the definition of test cases by sequence diagrams, both are converted into classification trees. From the classification trees we can finally generate SystemVerilog code. The methodology is introduced and evaluated by the example of an Adaptive Cruise Controller.

A systematic approach to the test of combined HW/SW systems

Today we can identify a big gap between requirement specification and the generation of test environments. This article extends the Classification Tree Method for Embedded Systems (CTM/ES) to fill this gap by new concepts for the precise specification of stimuli for operational ranges of continuous control systems. It introduces novel means for continuous acceptance criteria definition and for functional coverage definition.

Classification Trees for Random Tests and Functional Coverage

This article presents the classification tree method for functional verification to close the gap from the specification of a test plan to SystemVerilog (Chandra and Chakrabarty, 2001) test bench generation. Our method supports the systematic development of test configurations and is based on the classification tree method for embedded systems (CTM/ES) (Chakrabarty et al., 2000) extending CTM/ES for random test generation as well as for functional coverage and property specification

Systematic Model-in-the-Loop Test of Embedded Control Systems

Current model-based development processes offer new opportunities for verification automation, e.g., in automotive development. The duty of functional verification is the detection of design flaws. Current functional verification approaches exhibit a major gap between requirement definition and formal property definition, especially when analog signals are involved. Besides lack of methodical support for natural language formalization, there does not exist a standardized and accepted means for formal property definition as a target for verification planning. This article addresses several shortcomings of embedded system verification. An Enhanced Classification Tree Method is developed based on the established Classification Tree Method for Embeded Systems CTM/ES which applies a hardware verification language to define a verification environment.

Formal refinement and model checking of an echo cancellation unit

This article presents an approach, which combines theorem proving-based refinement with model checking for state based real-time systems. Our verification flow starts from UML state diagrams, which are translated to the formal B language and are model checked for real-time properties. By means of the B language and a B theorem prover, refined state diagrams are verified against their abstract representation. The approach is presented by means of the refinement of a digital echo cancellation unit.

Systematic Testbench Specification for Constrained Randomized Test and Functional Coverage

Functional Verification is well-accepted for Electronic System Level (ESL) based designs and is supported by a variety of standardized Hardware Verification Languages like PSL, e, and SystemVerilog. In this article, we present the classification tree method for functional verification (CTM/FV) as a novel method to close the gap from the verification plan to the specification of randomized tests and functional coverage for test configurations. CTM/FV is introduced based on graphical means from which we automatically generate SystemVerilog code as a testbench for constraint-based randomized tests and functional coverage, where concepts are outlined by the automotive example of an adaptive cruise controller.

Approach for a Formal Verification of a Bit-serial Pipelined Architecture

This paper presents a formal verification for a bit-serial hardware architecture. The developed architecture bases on the combination of different design paradigms and requires sophisticated design optimizations. The recently patented synchronous bit-serial pipelined architecture, which we investigate in this paper, is comprised of synchronous and systematic bit-serial processing operators without a central controlling instance. We add timing constraints at the boundaris of the architectures operators. To prove the validity of data synchronization we apply formal verification of the constraints on a cycle accurate representation of the implementation. The results of the formal verification is back annotated to the high-level model.