Achim Rettberg

Towards a Middleware Approach for a Self-configurable Automotive Embedded System

In this paper a middleware architecture for distributed automotive systems that supports self-configuration by dynamic load balancing of tasks is presented. The inclusion of self-configurability is able to offer reliability within the multimedia network of the vehicle (Infotainment). Load balancing of tasks could be applied if an error occurred within the network. The error detection in the network and the load balancing should run automatically. Therefore, the middleware architecture has to deal on one hand with the error detection and on the other hand with the migration of tasks. Additionally, to enable the migration it is important to identify the requirements of all electronic control units (ECU) and tasks within the network.

A Model-Based Approach for Executable Specifications on Reconfigurable Hardware

UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller.

Towards a Rigorous Modeling Formalism for Systems of Systems

The scope of this paper is collaborative, distributed safety critical systems which build up a larger scale system of systems (SoS). Systems participating in an SoS follow both global as well as individual goals, which may be contradicting. Both the global and local goals of the overall SoS may change over time. Hence, self-adaptive ness, i.e., reconfiguration of the SoS as a reaction on changes within its context is a major characteristic of this systems. The aim of this paper is to describe first steps towards a modeling formalism for SoS in a safety critical context. The challenge is to address on the one hand the required flexibility to adapt the system during run-time and on the other hand to guarantee that the system reacts still in a safe manner. To address these challenges, we propose an approach which guarantees that the system still reacts in a safe manner while adaption to uncertainty including context changes. This adaption has to be assumed as unsafe during design time. The key for having success is to define the interaction between the systems as well as its goals as basic elements of the design. Based on our former work, we propose a well-defined modeling approach for the interaction based on components as basic structural elements, the contract paradigm for the design of the interaction, and graph transformations, which addresses the adaptivity of system of systems. The component model is additionally explicitly enriched by goals, which supports so called evaluation functions to determine the level of target achievement.

TOWARDS RUN-TIME PARTITIONING OF A REAL TIME OPERATING SYSTEM FOR RECONFIGURABLE SYSTEMS ON CHIP

Reconfigurable computing have successfully been designed taking into advantage the supporting of architectures based on the FPGAs and CPU. Moreover, the new hybrid FPGAs (e.g. Virtex-II Pro™), provides a hardcore general-purpose processor (GPP) embedded into a field of programmable gate arrays. Together with the ability to be partially reconfigured, those chips are very attractive for implementation of run-time reconfigurable embedded systems. However, most of the efforts in this field were made in order to apply these capabilities at application level, leaving to the Operating System (OS) the provision of the necessary mechanisms to support these applications. This paper present an approach for run-time reconfigurable Operating System, which take advantage of the new hybrid FPGA chips to reconfigure itself based on online estimation of application demands. The paper focus on run-time assignment and reconfiguration of OS services over a hybrid architecture. The proposed model uses a 0-1 Integer programming strategy for assigning OS components over a hybrid architecture, as well as an alternative heuristic algorithm for it. In addition, the evaluation of the reconfiguration costs are presented and discussed.

Integrating Dynamic Load Balancing Strategies into the Car-Network

In this paper a middleware architecture for distributed automotive systems that supports dynamic load balancing of tasks is presented. Load balancing could be applied if an external device, like a PDA or mobile phone, is added to the vehicle network. This detection of the external device and the integration into the network should run automatically. Therefore, the middleware architecture has to deal with the fusion of such non-built-in devices. For the middleware, it is important to identify the requirements to support load balancing and the handling of external devices. By enriching the middleware with traditional load balancing strategies, an easy exchange of tasks could be realized.

A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems

The presented architecture has the peculiar feature of being self-timed and comprising a fully interlocked pipelining structure which aims at controlling the different computational paths of a system design. One example is the automotive industry where performance, space, cost, size, and weight are of vital importance, the main features of this architecture.

Design and Analysis of Distributed Embedded Systems

The main purpose of this paper is to discuss if the Unified Modeling Language (UML) can be used as a system-level language (SLL) for specifying embedded systems. in co-design environments. The requirements that a language has to fulfil to be considered as an SLL are presented and the advantages and disadvantages of using UML as an SLL are also indicated. The contribution of this paper consists on the explicit discussion of the key issues that must be taken into account when deciding if UML is to be used in a project as an SLL for embedded software.

Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking

The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task became very challenging. In this paper, a model-checking based approach will be described which allows us to guarantee timing bounds of multiple Synchronous Data Flow Graphs (SDFG) running on shared-bus multicore architectures. Our approach utilizes Timed Automata (TA) as a common semantic model to represent software components (SDF actors) and hardware components of the multicore platform. These TA are explored using the UPPAAL model-checker for providing the timing guarantees. Our approach shows a significant precision improvement compared with the worst-case bounds estimated based on maximal delay for every bus access. Furthermore, scalability is examined to demonstrate analysis feasibility for small parallel systems.

Analysis, Architectures and Modelling of Embedded Systems

Modelling.- State Machine Based Method for Consolidating Vehicle Data.- Automatic HW/SW Interface Modeling for Scratch-Pad and Memory Mapped HW Components in Native Source-Code Co-simulation.- Modelling of Device Driver Software by Reflection of the Device Hardware Structure.- An Infrastructure for UML-Based Code Generation Tools.- A Configurable TLM of Wireless Sensor Networks for Fast Exploration of System Communication Performance.- ConcurrenC: A New Approach towards Effective Abstraction of C-Based SLDLs.- Transaction Level Modelling.- Automatic Generation of Cycle-Approximate TLMs with Timed RTOS Model Support.- Transaction Level Modeling of Best-Effort Channels for Networked Embedded Devices.- Modeling Cache Effects at the Transaction Level.- Scheduling and Real-Time Systems.- Event Stream Calculus for Schedulability Analysis.- Real-Time Scheduling in Heterogeneous Systems Considering Cache Reload Time Using Genetic Algorithms.- Task-Dependent Processor Shutdown for Hard Real-Time Systems.- Experimental Evaluation of a Hybrid Approach for Deriving Service-Time Bounds of Methods in Real-Time Distributed Computing Objects.- Simulation, Verification and Test.- Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling.- Formal Verification for Embedded Systems Design Based on MDE.- Systematic Model-in-the-Loop Test of Embedded Control Systems.- Platforms and Processors.- Proteus, a Hybrid Virtualization Platform for Embedded Systems.- Constructing a Multi-OS Platform with Minimal Engineering Cost.- A Synchronization Method for Register Traces of Pipelined Processors.- Automotive Systems.- Development of Automotive Communication Based Real-Time Systems - A Steer-by-Wire Case Study.- Automatic Transformation of System Models in Automotive Electronics.- Towards a Load Balancing Middleware for Automotive Infotainment Systems.- Case Studies.- Towards an Irritable Bowel Syndrome Control System Based on Artificial Neural Networks.- A Hybrid Hardware and Software Component Architecture for Embedded System Design.- Low-Level Space Optimization of an AES Implementation for a Bit-Serial Fully Pipelined Architecture.- Wireless Sensor Networks.- The Case for Interpreted Languages in Sensor Networks.- Characterization of Inaccessibility in Wireless Networks: A Case Study on IEEE 802.15.4 Standard.- FemtoNode: Reconfigurable and Customizable Architecture for Wireless Sensor Networks.- Tutorials.- Efficient Modeling of Embedded Systems Using Computer-Aided Recoding.- New Challenges for Designers of Fault Tolerant Embedded Systems Based on Future Technologies.

Run-time reconfigurable RTOS for reconfigurable systems-on-chip

High computational performance and flexibility are the requirements of nowadays embedded systems and they are increasing constantly. Moreover, a single architecture must be able to support different applications with dynamically requirements (changing environments). Reconfigurable computing based on hybrid architectures, comprising general purpose processor (CPU) and Field Programmable Gate Array (FPGA), is very attractive because it can provide high computational performance as well as flexibility to support the requirements of todays embedded systems. As an Operating System (OS) is desired to provide support for such systems, it has to use the available resources in an optimal way (competing with the application), since an embedded system architecture usually lack of resources. Therefore, we present here our approach towards a reconfigurable RTOS that is able to distribute itself over a hybrid architecture (comprising FPGA and CPU). In this work we will present the main concepts and methods used to achieve the desired RTOS. Moreover, we present some preliminary evaluation results which show the applicability of our approach.