Alexander Wei Yin

Explorations of Honeycomb Topologies for Network-on-Chip

Rectangular mesh and torus are the mostly used topologies in network-on-chip (NoC) based systems. In this paper, we quantitatively illustrate that the honeycomb topology is an advantageous design alternative in terms of network cost which is one of the most important parameters that reflects both network performance and implementation cost. Comparing with the rectangular mesh and torus, honeycomb mesh and torus topologies lead to 40% decrease of the network cost. Then we explore the NoC related topological properties of both honeycomb mesh and torus topologies. By transforming the honeycomb topologies into rectangular brick shapes, we demonstrate that the honeycomb topologies are feasible to be implemented with rectangular devices. We also propose a 3D honeycomb topology since 3D IC has become an emerging and promising technique. Another contribution of this paper is the proposal of deadlock free routing algorithms. Based on either the concept of turn model or the logical network, deadlock free routing for all the discussed honeycomb topologies can be achieved.

Multi-application multi-step mapping method for many-core Network-on-Chips

Massive parallel computing performed on many-core Network-on-Chips (NoCs) is the future of the computing. One feasible approach to implement parallel computing is to deploy multiple applications on the NoC simultaneously. In this paper, we propose a multi-application mapping method starting with the application mapping which finds a region on the NoC for each application and then task mapping which maps all tasks of the application into each region. In the application mapping step, several strategies based on the maximal empty rectangle (MER) technique are introduced for finding an optimal region for each application. In the task mapping step, a tree-model based algorithm is used with the purpose of reducing the communication latency and energy consumption. The experiment results show that the proposed method can achieve considerable reduction of network latency and energy consumption (up to 18%) for a given set of applications.

A study of 3D Network-on-Chip design for data parallel H.264 coding

In this paper, we study and analyze different Network-on-Chip (NoC) designs for MPEG-4/H.264 coding. The encoding and decoding processes of H.264 have been analyzed. We discuss the parallelism of H.264, and an open-source encoding program is used as a case study. The contribution of this paper lies in the NoC design method and performance evaluation of data parallel H.264 coder. It is shown in our study that the inter-thread data dependency of shared reads and writes are performance bottlenecks. Different non-uniform cache access NoC designs have been explored. Two-dimensional (2D) and three-dimensional (3D) NoCs have been analyzed in terms of hop count and heat dissipation. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in two 3D NoC designs are reduced up to 34% compared with the 2D NoC. It is also shown that the heat dissipation is a trade-off consideration in improving the performance of 3D IC. Our analysis and experiment results provide a guideline to design efficient 3D NoCs for data parallel H.264 coding applications.

Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks

A feasible and scalable per-core DVFS architecture for on-chip network is presented. The supplies are dynamically adjusted at a very fine granularity based on the local traffic status. The adoption of multiple voltage supply networks and power selecting transistors provides the architecture with scala- bility and feasibility superior to existing similar techniques. With high-level simulation using 65nm power model obtained from widely-acknowledged tools, the effectiveness of the technique is demonstrated with quantitative analysis of energy overhead and latency penalty. Under various traffic patterns, the average flit energy is reduced considerably, ranging from 45% to 60%, with moderately increased but stable transmission latency.

Hierarchical agent based NoC with dynamic online services

As the size of NoCs increases, power consumption and fault/variation tolerance have become two of the most crucial problems for system designers. To address these problems, we propose a NoC architecture based on a hierarchy of monitoring agents. By tracing the circuit properties at run time, the agents at different architectural levels are able to monitor and control over the whole NoC platform. This monitoring approach partitions various online diagnostic and management services onto hierarchical implementation levels so as to provide scalability and variability for large-scale NoC design. This paper explains the monitoring interaction between agent levels, and focuses on system optimization alternatives handled by different agent levels. It further quantitatively analyzes the feasibility and design alternatives in monitoring communication interconnection upon regular tile-based NoC layout.

Comparison of mesh and honeycomb network-on-chip architectures

Rectangular Mesh is the most commonly used topology in the field of Network-on-Chip (NoC) due to its high regularity, symmetry and scalability. In this paper, we examine Honeycomb topology as another candidate for NoC architectures. Based on the simulations of Mesh and Honeycomb routers and network, we compare these two topologies in terms of power consumption, area cost and communication delay. Results show that Honeycomb topology outperforms Mesh by at least 25.9%, 54.2% and 30.0% in these three aspects.

EfiIoT: An efficient software architecture for internet of things

In the paper, we discuss a scalable, multi-purpose sensor network implementation called EfiIoT. It combines two network topologies to enhance scalability and introduce new uses, such as locally available data to subscribers. The system is designed to be put together from a variety of sensors. It supports almost any kind of user interface and supports many user bases with partially or wholly different data.

Change Function of 2D/3D Network-on-Chip

Network-on-Chip (NoC) has been widely accepted as one of the most promising on-chip communication architectures for many-core Systems-on-Chip (SoC). With billions of transistors integrated on a single chip, inter-component communication becomes more and more complicated and power hungry. By leveraging the existing technologies of computer networks, NoC enables the on-chip communication to be simpler and more predictable. With the unceasing increase of the number of on-chip components, issues such as communication delay, system throughput, power consumption and large die area start to emerge in traditional two dimensional (2D) integrated circuits (ICs). During the recent years, more attentions than ever have been focused on three dimensional (3D) ICs in both industry and academia. However, 3D ICs are known to have higher cost in several aspects, including heat dissipation, yield, testing, etc., than their 2D counterparts. In this paper, we propose a method based on the economic term of change function to analyze the profitability of using 3D rather than 2D NoCs. We compare the benefits and costs between 2D and 3D NoCs and judgments are made based on the quantized results of these comparisons.