Alexander Worm

Turbo-decoding without SNR estimation

Theoretically, it is necessary to estimate the SNR when using a MAP of the log-MAP constituent decoder. The effect of an SNR mismatch on the bit error rate performance of turbo-codes and the design of good variance estimators have been addressed by several authors. In this letter we study the SNR sensitivity of turbo-decoding with log-MAP and max-log-MAP constituent decoders respectively for AWGN and Rayleigh fading channels. Our theoretical and simulation results indicate that an estimation of the SNR is not necessary from a practical point of view. Our setup is aligned with decoder implementation aspects of future mobile communication systems.

A high-speed MAP architecture with optimized memory size and power consumption

This paper presents a novel high-speed maximum a posteriori (MAP) decoder architecture with optimized memory size and power consumption. Area and power consumption are both reduced significantly, compared to the state-of-the-art. The architecture is also capable of decoding recursive systematic convolutional codes which are the constituent codes of the revolutionary turbo-codes and related concatenation schemes. The architecture is highly scalable with respect to throughput, expanding its applicability over a wide range of throughput requirements (300 Mbit/s-45 Gbit/s and above).

Low power implementation of a turbo-decoder on programmable architectures

Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal architectures. Thus low power implementations of advanced channel decoding techniques are mandatory. In this paper we present a low power implementation of the most sophisticated channel decoding algorithm (Turbo-decoding) on programmable architectures. Low power optimization is performed on two abstraction levels: on system level by the use of an intelligent cancellation technique, on implementation level by the use of dynamic voltage scaling. With these techniques we can reduce the worst case is also applicable for hardware implementations. To the best of our knowledge, this is the first in-depth study of low power implementations of Turbo-decoders based on voltage scheduling for third generation wireless systems.

Influence of quantization on the bit-error performance of turbo-decoders

Turbo-codes are under consideration for third generation mobile communication systems. For any implementation of a turbo-decoder a fixed-point representation is mandatory. Usually, the bit-width of a fixed-point implementation has to be traded off versus its decoding performance. Past approaches towards a fixed-point representation show a degradation in performance. In this paper we apply a novel quantization methodology on turbo-decoders with (Max-)Log-MAP component decoders and present simulation results for both an AWGN and a Rayleigh fading channel model. The new quantization scheme leads to fixed-point implementations that do not degrade the bit-error performance. Under certain conditions it can even be slightly improved.

Implementation aspects of turbo-decoders for future radio applications

Turbo codes will most likely be employed in future radio systems as a channel coding scheme for high-rate data services. However, turbo decoding is a comparatively complex task. To obtain efficient decoder implementations, the system design space has to be explored on multiple levels. In this paper, we span the system design space for turbo codes and describe a method of exploration, while focusing on the implementation-dependent part. The design decisions taken during exploration are rated regarding complexity, throughput and power consumption. The second part of our paper evaluates sample software and hardware implementations of a 2 Mbit/s turbo decoder.

Design of low-power high-speed maximum a priori decoder architectures

Future applications demand high-speed maximum a posteriori (MAP) decoders. In this paper, we present an in-depth study of design alternatives for high-speed MAP architectures with special emphasis on low power consumption. We exploit the inherent parallelism of the MAP algorithm to reduce power consumption on various abstraction levels. A fully parameterizable architecture is introduced which allows us to optimally adapt the architecture to the application requirements and the throughput. Intensive design space exploration has been carried out on a state-of-the-art 0.2 /spl mu/m technology, including efficient parallelism techniques, a data flow transformation for reduced power consumption, and an optimized FIFO implementation.

Performance of low complexity turbo-codes in the UTRA-TDD-mode

In the project FRAMES (Future Radio Wideband Multiple Access Systems) of the European research program ACTS (Advanced Communications Technologies and Services) an air interface proposal for UMTS (Universal Mobile Telecommunications System) has been developed. In January 1998 ETSI (European Telecommunications Standards Institute) reached a consensus on a UMTS air interface standard termed UTRA (UMTS Terrestrial Radio Access), which is mainly based on the proposal developed within FRAMES. UTRA consists of an FDD (frequency division duplex) mode applying the multiple access scheme W-CDMA (wideband CDMA) and a TDD (time division duplex) mode applying the multiple access scheme TD-CDMA (time division CDMA). For the different services to be supported a set of channel coders has been proposed which have to be further evaluated. In consideration of this need, in this paper a low-complexity rate-compatible punctured turbo code (RCPTC) for high-quality circuit switched data services in the TDD-mode is investigated depending on its main parameters. The criterion in these investigations is the bit error ratio (BER). The performance of the considered turbo code (TC) is analyzed and compared to a convolutional code (CC) of equal complexity.