Frank Gilbert

A scalable system architecture for high-throughput turbo-decoders

The need for higher data rates is ever rising as wireless communications standards move from the third to the fourth generation. Turbo-Codes are the prevalent channel codes for wireless systems due to their excellent forward error correction capability. So far research has mainly focused on components of high throughput Turbo-Decoders. In this paper we explore the Turbo-Decoder design space anew, both under system design and deep-submicron implementation aspects.Our approach incorporates all levels of design, from I/O behavior down to floorplaning taking deep-submicron effects into account. Its scalability allows to derive optimized architectures tailored to the given throughput and target technology. We present results for 3GPP compliant Turbo-Decoders beyond 100 Mbit/s synthesized on a 0.18 μm standard cell library.

Optimized concurrent interleaving architecture for high-throughput turbo-decoding

Future applications of turbo-codes will demand higher throughput than the currently envisioned 2 Mbit/s for 3rd generation wireless communication. Several approaches have already been made to design high throughput component decoders. The interleavers which separate the component decoders, however, have not yet gained much attention, although they form a severe data transfer bottleneck. Based on our previous work, which demonstrated how to widen the interleaver bottleneck through concurrent interleaving, we present in this paper a new architecture optimized with respect to routing and interconnect properties of deep-submicron technologies. Our interconnect driven design approach leads to simplified local interleaver cells with almost negligible control flow. No global routing nor global control is necessary. A parameterizable VHDL model was developed for profiling and synthesis under the 3GPP scenario using different degrees of parallelization.

Concurrent interleaving architectures for high-throughput channel coding

Interleavers are widely used for a vast range of communications applications. Traditionally used for burst-error separation in distorted channels, they have gained additional interest since the discovery of turbo codes whose performance essentially depends on the interleavers. With the ever increasing data rates demanded by customers, architectures that provide interleaving at high throughput become mandatory. We present an heuristic approach to the design of interleaving architectures based on random graph generation. They can handle any given interleaver pattern and allow for any parallelization degree, and hence speed-up, of the interleaving operation. Moreover, this enables highly parallel architectures for channel decoders such as turbo- and LDPC-decoders.

Low complexity stopping criteria for UMTS turbo-decoders

Turbo-codes are part of the third generation wireless communications system (UMTS). A turbo-decoder consists of two soft-in soft-out component decoders, which exchange information (soft-values) in an iterative process. The number of iterations for decoding strongly depends on the channel characteristic which can change from block to block due to fading. In this paper, we present two new stopping criteria which can be implemented on dedicated hardware or DSP with negligible overhead. The new criteria operate on the sum of the absolute soft output values, calculated after each component decoder and is referred to as sum reliability. We compare the communications performance and average number of iterations of our proposed criteria to other criteria in literature using a fixed-point 8-state turbo-decoder implementation in an UMTS FDD-downlink chain. An analysis of the arithmetic complexity and memory demand yields minimal overhead with excellent performance compared to other stopping criteria.

Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors

Software implementations of channel decoding algorithms are attractive for communication systems with their large variety of existing and emerging standards due to their flexibility and extensibility. For high throughput, however, a single processor can not provide the necessary computing power. Using several processors in parallel, without exploiting the internal parallelism of the algorithm, leads to intolerable overhead in area, power consumption, and latency. We propose a multiprocessor based turbo-decoder implementation where inherently parallel decoding tasks are mapped onto individual processing nodes. The implied challenging inter-processor communication is efficiently handled by our framework such that throughput is not degraded. In this paper, we present communication centric architectures from buses to heterogenous networks that allow us to interconnect numerous processors to perform high throughput turbo-decoding.

Low power implementation of a turbo-decoder on programmable architectures

Low Power is an extremely important issue for future mobile radio systems. Channel decoders are essential building blocks of base-band signal processing units in mobile terminal architectures. Thus low power implementations of advanced channel decoding techniques are mandatory. In this paper we present a low power implementation of the most sophisticated channel decoding algorithm (Turbo-decoding) on programmable architectures. Low power optimization is performed on two abstraction levels: on system level by the use of an intelligent cancellation technique, on implementation level by the use of dynamic voltage scaling. With these techniques we can reduce the worst case is also applicable for hardware implementations. To the best of our knowledge, this is the first in-depth study of low power implementations of Turbo-decoders based on voltage scheduling for third generation wireless systems.

Evaluation of algorithm optimizations for low-power Turbo-Decoder implementations

Energy aware and low-power implementation of Turbo-Decoders are a must for 3GPP and other communication system designs. This paper explores a reduced-search maximum-a-posteriori algorithm usually referred to as a low-power strategy for implementation. Synthesis results indeed show a noticeable power saving potential in the absence of iteration control. In the presence of iteration control, however, this paper shows that it even leads to an increased power consumption.

Designing for Xilinx XC6200 FPGAs

With the XC6200 FPGA Xilinx introduced the first commercially available FPGA designed for reconfigurable computing. It has a completely new internal architecture, so new design algorithms and software is needed. Due to the fact that most applications are in the research area, the number of sold units seems to be small. Because of this progress of design tools for this architecture is rather low. This paper discusses the problems, which appear during designing for the XC6200 FPGAs. A dedicated design flow is presented and demonstrated on an example application.

Architecture-driven voltage scaling for high-throughput turbo-decoders

The outstanding forward error correction provided by Turbo-Codes made them part of todays and emerging communications standards. Therefore, efficient Turbo-Decoder architectures are important building blocks in communications systems. In this paper we present a scalable, highly parallel architecture for UMTS compliant Turbo decoding and apply architecture-driven voltage scaling to reduce the energy consumption. We will show that this approach adds some additional, more energy-efficient solutions to the design space of low power Turbo decoding systems. It can save up to 34% of the decoding energy per datablock under realistic voltage assumptions. We present throughput, area, and energy results for various degrees of parallelization based on synthesis on a 0.18 μm ASIC-technology library, which is characterized for two different supply voltages: nominal 1.8 V and nominal 1.3 V.