Alexandre Malherbe

On-Chip Voltage Regulator Protecting Against Power Analysis Attacks

The on-chip voltage regulator proposed in this paper has been specifically developed for smart cards. Its purpose is to protect the supplied system against power analysis attacks. It allows to generate the internal power supply voltage from the external power supply voltage provided by card readers, while ensuring the uncorrelation between the external power supply current and the internal power supply current. The power supply current of an electronic system can be decomposed into a DC component, which contains little information, and an AC component, which handles considerably more. In order to reach a good compromise between regulation and security, while respecting the smart card stringent technological constraints, these two components are treated separately by a bi-channel power structure. The presented implementation has been simulated from the process parameters of a STMicroelectronics 0.18 mum CMOS technology. It allows to generate a 1.8 V output voltage from a 2 to 5.5 V input voltage range. The structure has been sized to handle a 25 mA DC current while hiding a 20 MHz AC current presenting 75 mA peaks. Its estimated area is approximatively 0.8 mm2.

Sub-1V Oguey's Current Reference Without Resistance

The circuit proposed in this paper allows to generate a sub-1V 50 nA current reference. By changing the inversion mode of two transistors, the original Ogueys structure becomes compliant with ultra low voltage requirements, while preserving the topology inherent simplicity, guarantee of low cost. Furthermore, the use of EKV2.0 MOS model involves an inversion level free study. As a consequence, supply voltage and/or silicon area can be optimized unambiguously in regards to current target and technology. Simulation with a higher than 500 mV Vt technology, for an inversion level of only 2.78, gives a minimum supply voltage of 710 mV.

Best compromise between tele supply and modulated rate of back scattered signal in RFID system

Emerging applications of contact less smart card operating at 13.56 MHz like video transmission and ICAO e-passport need high data rates. This study focuses on the communication from the deported element (batteryless smartcard or transponder) to the reader. In order to limit the cost of the transponders, most of the time, smart cards are batteryless. The chip is connected to an antenna and is supplied by the power coming from the induced voltage of the coupled antennas. Designers have to deal with a compromise between best chip supply and best load modulation. The purpose of this paper is to present a new method to compute the best load to switch for a given power supply. For this supply, the best modulation degree of the back scattered signal will be reached. The theoretical results and the simulation results will be compared to measurements.

Versatile macromodel for the power supply of submicronic CMOS microprocessors based on voltage down DC-DC converter

A new SPICE macromodel that simulates a microprocessor loading impedance at the power supply is presented. This macro model has been especially created to accelerate the time to market in the design of DC-DC voltage converters used to supply submicronic digital integrated circuits. The proposed macromodel has been successfully compared to measurements for a dedicated test-chip implemented in CMOS 0.35 /spl mu/m from STM. The test-chip includes a 16 bit microprocessor supplied by a voltage down converter. SPICE simulations and measurements demonstrate the efficiency of the proposed model.