Benjamin Duval

A new oscillator-based Random Number Generator

This paper proposes a low power, Truly Random Number Generator (TRNG) intended for a RFID tag application. We present here a new approach of the oscillator-based TRNG. The circuit relies on a system of jittered clocks that are being monitored by a clock arbiter-synchroniser, in order to have a random output signal without the use of a high speed jittered oscillator technique, that implies a significative increase the total power budget and a reduction in the output frequency. The system under study will be developed in AMS 0.35μm standard process for a 3.0V supply.

Sub-1V Oguey's Current Reference Without Resistance

The circuit proposed in this paper allows to generate a sub-1V 50 nA current reference. By changing the inversion mode of two transistors, the original Ogueys structure becomes compliant with ultra low voltage requirements, while preserving the topology inherent simplicity, guarantee of low cost. Furthermore, the use of EKV2.0 MOS model involves an inversion level free study. As a consequence, supply voltage and/or silicon area can be optimized unambiguously in regards to current target and technology. Simulation with a higher than 500 mV Vt technology, for an inversion level of only 2.78, gives a minimum supply voltage of 710 mV.

Discrete chaos - based Random Number Generator

This paper presents a low power True Random Number Generator (TRNG), based on the discrete time-chaos, intended for a RFID security applications, to be developped on CMOS 350nm standard technology. The circuit relies on a discrete time chaotic oscillator to generate patterns to be sampled to get a raw random signal to be debiased by a digital corrector.

Chaos Based Random Clock Generator

The integrated analog system proposed in this paper allows to generate a high entropy random clock signal. It is based on the biasing of an oscillator by a random stair-step current. The step amplitude varies randomly on a continuous, uniformly distributed and width-tunable interval. The step length varies randomly on a continuous interval presenting an average adjustable value. The clock signal thus generated presents frequency jumps between random frequencies, occurring at random instants. Its average frequency is tunable and its frequency variation range is continuous, uniformly distributed and width- adjustable. The proposed implementation uses a chaotic oscillator exhibiting a double-scroll attractor as entropy source. It has been simulated from the process parameters of a STMicroelectronics 0.18 mum CMOS technology. It consumes less than 1 mW for a frequency variation range centered on 20 MHz and extending symmetrically on 30 MHz. Its characteristics deviation over process, voltage and temperature (PVT) variations is less than 10%. Its estimated area is approximatively 0.01 mm2.

Moderate inversion: highlights for low voltage design

This paper proposes to use a non conventional mode of operation to meet low voltage constraints: The moderate inversion. EKV 2.0 MOS model provides hand calculation applicable equations, while a BSIM3v3 simulation model is sufficiently accurate to design static circuits. The self cascode structure studied with highlights of the EKV 2.0 MOS model is revealed to be linear with temperature from weak to strong inversion: simulation and experimental data are provided. This self cascode linear with temperature voltage reference is the starting point of a new self biased current reference: An all in moderate inversion exemple is given, and simulation results are provided.