Alexandre Mercat

Implementation of a Stereo Matching algorithm onto a Manycore Embedded System

Stereo Matching techniques aim at reconstructing the disparity maps with a pair of images. The use of Stereo Matching techniques in embedded systems is very challenging due to the complexity of the state of the art algorithms. This paper proposes a real-time Stereo Matching algorithm optimised for the last generation of Manycore Embedded Systems. The features and parameters of the algorithms have been chosen to optimise the trade-off between an high quality and a low complexity. A memory analysis is performed for the algorithms decomposition and the resulting mapping on the Manycore platform is provided. Algorithm and arithmetic optimisations have been applied to each part of the algorithm to decrease the execution time down to 160ms for a CIF resolution.

Energy reduction opportunities in an HEVC real-time encoder

High Efficiency Video Coding (HEVC) is one of the latest released video standards and offers up to 40% bitrate savings when compared to the widespread H.264/AVC standard, at the cost of a substantial complexity growth. Constraining the complexity of HEVC encoding is a challenging task for embedded applications based on a software encoder. In the last few years, the Internet of Thingss (IoTs) has become a reality. Forecoming applications are likely to boost mobile video demand to an unprecedented level. In this context, designing energy-efficient HEVC real-time encoders is becoming a major challenge for software and hardware designers. In this paper, an analysis is conducted of the energy reduction opportunities offered by an HEVC encoder. The energy reduction search space is demonstrated, and the impact on energy consumption of encoding tools at various levels of granularity is measured.

Optimized Belief Propagation Algorithm onto Embedded Multi and Many-Core Systems for Stereo Matching

Stereo matching techniques aim at reconstructing disparity maps from a pair of images. The use of stereo matching techniques in embedded systems is very challenging due to the complexity of the state-of-the-art algorithms. Local stereo matching algorithms are efficiently implemented on GPU and DSP. This paper presents the optimization of the One Dimension Belief Propagation (BP-1D) algorithm. BP-1D is faster than previous algorithms on monocore DSP and its implementation onto multicore DSPs is straightforward. BP-1D implemented on multicore embedded platforms out-performs previous stereo matching implementations reaching real-time performances for resolutions up to 1080p with a 10 Watts power consumption.

Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice

Current trends in high performance and embedded computing include design of increasingly complex hardware architectures with high parallelism, heterogeneous processing elements, and nonuniform communication resources. In order to take hardware and software design decisions, early evaluations of the system nonfunctional properties are needed. These evaluations of system efficiency require electronic system-level information on both algorithms and architecture. Contrary to algorithm models for which a major body of work has been conducted on defining formal models of computation (MoCs), architecture models from the literature are mostly empirical models from which reproducible experimentation requires the accompanying software. In this paper, a precise definition of a model of architecture (MoA) is proposed that focuses on reproducibility and abstraction and removes the overlap previously existing between the notions of MoA and MoC. A first MoA, called the linear system-level architecture model (LSLA), is presented. To demonstrate the generic nature of the proposed new architecture modeling concepts, we show that the LSLA model can be integrated flexibly with different MoCs. LSLA is then used to model the energy consumption of a state-of-the-art multiprocessor system-on-chip (MPSoC) when running an application described using the synchronous dataflow MoC. A method to automatically learn LSLA model parameters from platform measurements is introduced. Despite the high complexity of the underlying hardware and software, a simple LSLA model is demonstrated to estimate the energy consumption of the MPSoC with a fidelity of 86%.

Prediction of quad-tree partitioning for budgeted energy HEVC encoding

High Efficiency Video Coding (Hevc), the newest video encoding standard, provides up to 50% bitrate savings compared to the state-of-art H.264/AVC standard for the same perceptual video quality. In the last few years, the Internet of Things (IoT) has become a reality. Forthcoming applications are likely to boost mobile video demand to an unprecedented level. A large number of systems are likely to integrate HEVC codec in the long run and will need to be energy aware. In this context, constraining the energy consumption of HEVC encoder becomes a challenging task for embedded applications based on a software encoder. The most frequent approach to overcome this issue consists in optimising the coding tree structure to balance compression efficiency and energy consumption. In the purpose of budgeting the energy consumption of real-time HEVC encoder, we propose in this paper a variance-aware quad-tree prediction to limit the recursive RDO process. The experimental results show that the proposed energy reduction scheme achieve on average 60% of energy reduction for a slight bit rate increase of 3.4%.

Constrain the Docile CTUs: An In-Frame complexity allocator for HEVC Intra encoders

High Efficiency Video Coding (HEVC) is one of the latest released video standards and offers up to 40% bitrate savings when compared to the widespread H.264/AVC standard, at the cost of a substantial complexity growth. Constraining the complexity of HEVC encoding is a challenging task for embedded applications based on a software encoder. The most frequent approach to solve this problem is to optimise the coding tree structure to balance compression efficiency and computational complexity. In this context, we propose and assess a method to adequately allocate the computational complexity among coding units in a frame encoded in Intra mode. By studying an open-source real-time HEVC encoder, correlations are observed between Rate-Distortion (RD)-cost and encoding complexity that motivate a new complexity allocation technique. This technique, called “Constrain the Docile CTUs” (CDC), consists of allocating less computational complexity to units with low RD-costs and using RD-costs from preceding images as predictors for the current RD-costs. Experimental results demonstrate substantial gains, up to 36% of Bjøntegaard Delta Bit Rate (BD-BR), when using CDC method instead of other allocation methods.

On predicting the HEVC intra quad-tree partitioning with tunable energy and rate-distortion

Future evolutions of the Internet of Things (IoT) are likely to boost mobile video demand to an unprecedented level. A large number of battery-powered systems will then integrate an High Efficiency Video Coding (Hevc) codec, implementing the latest video encoding standard from MPEG, and these systems will need to be energy efficient. Constraining the energy consumption of Hevc encoders is a challenging task, especially for embedded applications based on software encoders. The most efficient approach to manage the energy consumption of an Hevc encoder consists of optimizing the quad-tree partitioning and balance compression efficiency and energy consumption. The quad-tree partitioning splits the image into encoding units of variable sizes. The optimal size for a unit is content dependent and affects the encoding efficiency. Finding this optimal repartition is complex and the energy required by the so-called rate-distortion optimization (RDO) process dominates the encoder energy consumption. For the purpose of budgeting the energy consumption of a real-time Hevc encoder, we propose in this paper a variance-aware quad-tree prediction that limits the energetic cost of the RDO process. The predictor is moreover adjustable by two parameters,

Smart search space reduction for approximate computing: A low energy HEVC encoder case study

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