Luca Maggiani

Reconfigurable FPGA architecture for computer vision applications in Smart Camera Networks

Smart Camera Networks (SCNs) is nowadays an emerging research field which represents the natural evolution of centralized computer vision applications towards full distributed and pervasive systems. In such a scenario, one of the biggest effort is in the definition of a flexible and reconfigurable SCN node architecture able to remotely support the possibility of updating the application parameters and changing the running computer vision applications at run-time. In this respect, this paper presents a novel SCN node architecture based on a device in which a microcontroller manages all the network functionality as well as the remote configuration, while an FPGA implements all the necessary module of a full computer vision pipeline. In the paper the envisioned architecture is first detailed in general terms, then a real implementation is presented to show the feasibility and the benefits of the proposed solution. Finally, performance evaluation results prove the potential of hardware software codesign in reaching flexibility and reduced latency time.

Reconfigurable architecture for computing histograms in real-time tailored to FPGA-based smart camera

The design and development of distributed innovative services leveraging pervasive smart camera network solutions requires the use of reconfigurable low-cost smart cameras. In this respect, FPGA based Smart Cameras enabled to wireless communication that follow the Internet of things paradigm are a promising solution. The paper proposes an optimized design of the histogram extractor algorithm targeted to low-complexity and low-cost FPGA based Smart Cameras. The proposed solution is the basis for a wide range of distributed computer vision applications. We first define a general architecture for the image histogram core, then we evaluate its performance with a real implementation.

Distributed coordination model for smart sensing applications

Distributed networks of smart sensors are nowadays representing the frontier of Machine-to-Machine (M2M) interoperability. In such a scenario several challenges must be addressed in order to create effective solutions. Coordination among nodes to satisfy monitoring purposes while addressing network constraints is considered of utmost importance. In this respect, the paper proposes a novel coordination model for self-organizing smart monitoring systems. The proposed algorithm is able to autonomously retrieve event correlations from the environment in order to coordinate the nodes. By relying on temporal and spatial correlations, the proposed system can be particularly suited for Smart Camera Network (SCN) deployments where multiple cameras monitor distributed targets. Along the algorithm definition, the paper presents a performance evaluation of the proposed approach through simulations, thus evaluating the robustness of the proposed model against message losses.

HOG-Dot: A Parallel Kernel-Based Gradient Extraction for Embedded Image Processing

In this letter, we propose HOG-Dot, a method for the direct computation of the polar image gradients coordinates from the pixels values. The proposed algorithm, to be used as the first step of the Histogram of Oriented Gradient (HOG) pipeline, approximates the exact gradient with its projection onto a versor chosen among the projection plane set. Instead of non linear computations, the HOG-Dot method exploits linear operations while introducing a bounded approximation error with respect to other HOG approaches, thus resulting a more suitable solution for embedded devices. Concerning the state of the art, it also achieves improved accuracy with the mathematical spatial gradient formulation .

Towards softwarization in the IoT: Integration and evaluation of t-res in the oneM2M architecture

Softwarization is a systemic trend which appears under several paradigms impacting networks, services and terminals evolution. Even the Internet of Things (IoT) scenario is going to be affected by this revolution. The efforts that are being made to provide IoT objects with embedded logic reconfiguration capabilities and the architectures that are being defined to support standard Machine-2-Machine (M2M) transactions are clear expressions of this trend. In this direction, a powerful framework to enable softwarization in constrained IoT objects is T-Res, where a virtual-machine based design is used to support execution tasks abstraction. To adopt T-Res in a real scenario in which device software functionalities can be remotely managed in an automatic fashion, its integration in a global M2M architecture must be defined. In this paper, the integration of TRes in the oneM2M architecture is presented, and its feasibility concerning application logic execution time and power consumption is analyzed by taking into account new generation devices. Performance results show that although oneM2M compliant TRes requires greater execution times and energy consumption when compared to a monolithic firmware approach, it results to be a feasible solution to be implemented in current and next generation IoT objects in order to provide advanced application logic reconfigurability features in softwarized ecosystems.

Lightweight error correction technique in industrial IEEE802.15.4 networks

Industrial Wireless Sensor Networks (IWSNs) are nowadays becoming more and more popular thanks to their flexibility and pervasive monitoring capabilities to support process automation and remote maintenance applications. In such a scenario, channel errors due to the wireless medium can result in data packet losses, and consequently in unreliable IWSN services. To mitigate the above reported problem, this paper presents a lightweight error correction scheme specially developed for IEEE802.15.4-based IWSNs. By adding error correction and detection information inside the IEEE802.15.4 MAC data frame, the proposed FEC scheme is able to guarantee a backward compatibility with the standard while providing advanced capabilities in recovering data packets affected by bit errors. In the paper the benefits of the proposed technique are first evaluated through simulated loss traces, then they are validated in a real environment by considering real loss traces collected in an electricity power plant. The proposed error correction scheme is able to recover around 50% of the data packets that would be lost in case of a standard communication without any error correction capability.

Parallel image gradient extraction core for FPGA-based smart cameras

One of the biggest efforts in designing pervasive Smart Camera Networks (SCNs) is the implementation of complex and computationally intensive computer vision algorithms on resource constrained embedded devices. For low-level processing FPGA devices are excellent candidates because they support massive and fine grain data parallelism with high data throughput. However, if FPGAs offers a way to meet the stringent constraints of real-time execution, their exploitation often require significant algorithmic reformulations. In this paper, we propose a reformulation of a kernel-based gradient computation module specially suited to FPGA implementations. This resulting algorithm operates on-the-fly, without the need of video buffers and delivers a constant throughput. It has been tested and used as the first stage of an application performing extraction of Histograms of Oriented Gradients (HOG). Evaluation shows that its performance and low memory requirement perfectly matches low cost and memory constrained embedded devices.

Models of Architecture: Reproducible Efficiency Evaluation for Signal Processing Systems

The current trend in high performance and embedded signal processing consists of designing increasingly complex heterogeneous hardware architectures with non-uniform communication resources. In order to take hardware and software design decisions, early evaluations of the system non-functional properties are needed. These evaluations of system efficiency require high-level information on both the algorithms and the architecture. In this paper, we define the notion of Model of Architecture (MoA) and study the combination of a Model of Computation (MoC) and an MoA to provide a design space exploration environment for the study of the algorithmic and architectural choices. A cost is computed from the mapping of an application, represented by a model conforming a MoC onto an architecture represented by a model conforming an MoA. The cost is composed of a processing-related part and a communication-related part. It is an abstract scalar value to be minimized and can represent any non-functional requirement of a system such as memory, energy, throughput or latency.

Design productivity of a high level synthesis compiler versus HDL

The complexity of hardware systems is currently growing faster than the productivity of system designers and programmers. This phenomenon is called Design Productivity Gap and results in inflating design costs. In this paper, the notion of Design Productivity is precisely defined, as well as a metric to assess the Design Productivity of a High-Level Synthesis (HLS) method versus a manual hardware description. The proposed Design Productivity metric evaluates the trade-off between design efficiency and implementation quality. The method is generic enough to be used for comparing several HLS methods of different natures, opening opportunities for further progress in Design Productivity. To demonstrate the Design Productivity evaluation method, an HLS compiler based on the CAPH language is compared to manual VHDL writing. The causes that make VHDL lower level than CAPH are discussed. Versions of the sub-pixel interpolation filter from the MPEG HEVC standard are implemented and a design productivity gain of 2.3× in average is measured for the CAPH HLS method. It results from an average gain in design time of 4.4× and an average loss in quality of 1.9x.

DreamCAM: A FPGA-based platform for smart camera networks

The main challenges in smart camera networks come from the limited capacity of network communications. Indeed, wireless protocols such as the IEEE 802.15.4 protocol target low data rate, low power consumption and low cost wireless networking in order to fit the requirements of sensor networks. Since nodes more and more often integrate image sensors, network bandwidth has become a strong limiting factor in application deployment. This means that data must be processed at the node level before being sent on the network. In this context, FPGA-based platforms, supporting massive data parallelism, offer large opportunities for on-board processing. We present in this paper our FPGA-based smart camera platform, called DreamCam, which is able to autonomously exchange processed information on an Ethernet network.