Alfonso Troya

Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture

In this paper, we proposed a novel Coordinate Rotation Digital Computer (CORDIC) rotator algorithm that converges to the final target angle by adaptively executing appropriate iteration steps while keeping the scale factor virtually constant and completely predictable. The new feature of our scheme is that, depending on the input angle, the scale factor can assume only two values, viz., 1 and 1//spl radic/2, and it is independent of the number of executed iterations, nature of iterations, and word length. In this algorithm, compared to the conventional CORDIC, a reduction of 50% iteration is achieved on an average without compromising the accuracy. The adaptive selection of the appropriate iteration step is predicted from the binary representation of the target angle, and no further arithmetic computation in the angle approximation datapath is required. The convergence range of the proposed CORDIC rotator is spanned over the entire coordinate space. The new CORDIC rotator requires 22% less adders and 53% less registers compared to that of the conventional CORDIC. The synthesized cell area of the proposed CORDIC rotator core is 0.7 mm/sup 2/ and its power dissipation is 7 mW in IHP in-house 0.25-/spl mu/m BiCMOS technology.

On the single-chip implementation of a Hiperlan/2 and IEEE 802.11a capable modem

Broadband wireless communication is the key technology to a new generation of products in the consumer market. The emerging standards for the 5 GHz band will form the basis for many applications requiring a high communication bandwidth. Low cost and low power dissipation will be a prerequisite for most mobile applications. One way to realize low-cost systems is to reduce the system complexity and deploy highly integrated components. The work presented in this article discusses aspects of implementing a complete Hiperlan/2 and IEEE 802.11a compliant modem, including the physical layer as well as the data link control layer, into a single chip.

Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems

In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and their implementation. Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arc tangent computation unit, numerically controlled oscillator, and the decimation filters. The use of multiple clock domains and clock gating reduces the power consumption further. These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25mum- 5-metal layer BiCMOS technology from Institute for High Performance Microelectronics.

Optimized low-power synchronizer design for the IEEE 802.11a standard

The authors propose a low-power synchronizer design for the IEEE 802.11a standard capable to estimate frequency offsets in the range /spl plusmn/468 kHz (80 ppm @ 5.8 GHz) with very simple and effective frame detection and timing synchronization. The core area of the design after layout is 13 mm/sup 2/, including the CORDIC and FFT processors, with a total estimated power consumption of 140 mW.

Efficient Inner Receiver Design for OFDM-Based WLAN Systems: Algorithm and Architecture

In this article we propose a complete solution for the so-called inner receiver of an OFDM-WLAN system based on the IEEE 802.11a standard. We concentrate our investigations on three key components forming the inner receiver namely, the synchronizer, the channel estimator and the digital timing loop. The main goal is the joint optimization of the signal processing algorithms along with the implementation friendly VLSI architecture required for these three key components in order to reduce power, area and latency, without compromising the performance excessively. We provide both the mathematical details and extensive computer simulations to validate our design

A CORDIC like processor for computation of arctangent and absolute magnitude of a vector

In this paper, we propose a CoOrdinate Rotation DIgital Computer (CORDIC) like processor for computing absolute magnitude of a vector and its corresponding phase angle. It does not require the scale factor compensation step and addition/subtraction operation along the z datapath, has a convergence range over the entire coordinate space and shows similar error characteristics as that of the conventional CORDIC. The synthesis result shows that the proposed processor is hardware economic and suitable for low power applications.

Simplified residual phase correction mechanism for the IEEE 802.11a standard

It is of common use in OFDM transmission to define some of the sub-carriers as pilots. These sub-carriers contain information, which is known a priori at the receiver and are typically used for channel estimation. In the special case of the IEEE 802.11a standard, the pilots cannot be used for channel estimation because of their wide separation in the frequency domain. However, they are useful to track phase variations remaining after synchronization during reception of a frame. In this paper we propose a very simple mechanism to estimate and correct these phase variations using the pilots. We also present a channel estimator necessary to support such a simplified mechanism.

On the implementation of a low-power IEEE 802.11a compliant Viterbi decoder

This article describes a standard cell based novel implementation of a low-power Viterbi decoder (VD) targeted for the IEEE 802.11a wireless LAN system. Multiple clock rates have been used to reduce the power consumption and the inherent bandwidth mismatch between the add-compare-select (ACS) and traceback operations. Aggressive clock gating and innovative circuit techniques reduce the power consumption further. The normalized cell area and dynamic power consumption of the designed VD are 5.9 mm/sup 2/ and 53 mW respectively. The normalized power dissipation of the VD is 0.66 mW/Mbps.

Implementation of an IEEE 802.11a compliant low-power baseband processor

In this paper results of an IEEE 802.11a compliant low-power baseband processor implementation are presented. The detailed structure of the baseband processor and its constituent blocks is given. Additionally, the design flow is briefly described and synthesis and layout results are reported.

A 16-bit CORDIC rotator for high-speed wireless LAN

We propose a novel 16-bit low power CORDIC rotator that is used for high-speed wireless LAN. The algorithm converges to the final target angle by adaptively selecting appropriate iteration steps while keeping the scale factor virtually constant. The VLSI architecture of the proposed design eliminates the entire arithmetic hardware in the angle approximation datapath and reduces the number of iterations by 50% on an average. The cell area of the processor is 0.7 mm and it dissipates 7 mW power at 20 MHz frequency.