Koushik Maharatna

50 Years of CORDIC: Algorithms, Architectures, and Applications

Year 2009 marks the completion of 50 years of the invention of CORDIC (coordinate rotation digital computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift-add operations, it can perform several computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division, square-root, solution of linear systems, eigenvalue estimation, singular value decomposition, QR factorization and many others. As a consequence, CORDIC has been utilized for applications in diverse areas such as signal and image processing, communication systems, robotics and 3-D graphics apart from general scientific and technical computation. In this article, we present a brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications.

A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM

In this paper, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in an OFDM-based IEEE 802.11a wireless LAN baseband processor. The 64-point FFT is realized by decomposing it into a two-dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64-point FFT/IFFT processor has been fabricated and tested successfully using our in-house 0.25-/spl mu/m BiCMOS technology. The core area of this chip is 6.8 mm/sup 2/. The average dynamic power consumption is 41 mW at 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption.

A Low-Complexity ECG Feature Extraction Algorithm for Mobile Healthcare Applications

This paper introduces a low-complexity algorithm for the extraction of the fiducial points from the electrocardiogram (ECG). The application area we consider is that of remote cardiovascular monitoring, where continuous sensing and processing takes place in low-power, computationally constrained devices, thus the power consumption and complexity of the processing algorithms should remain at a minimum level. Under this context, we choose to employ the discrete wavelet transform (DWT) with the Haar function being the mother wavelet, as our principal analysis method. From the modulus-maxima analysis on the DWT coefficients, an approximation of the ECG fiducial points is extracted. These initial findings are complimented with a refinement stage, based on the time-domain morphological properties of the ECG, which alleviates the decreased temporal resolution of the DWT. The resulting algorithm is a hybrid scheme of time- and frequency-domain signal processing. Feature extraction results from 27 ECG signals from QTDB were tested against manual annotations and used to compare our approach against the state-of-the art ECG delineators. In addition, 450 signals from the 15-lead PTBDB are used to evaluate the obtained performance against the CSE tolerance limits. Our findings indicate that all but one CSE limits are satisfied. This level of performance combined with a complexity analysis, where the upper bound of the proposed algorithm, in terms of arithmetic operations, is calculated as 2.423N+214 additions and 1.093N+12 multiplications for N ≤ 861 or 2.553N+102 additions and 1.093N+10 multiplications for N > 861 (N being the number of input samples), reveals that the proposed method achieves an ideal tradeoff between computational complexity and performance, a key requirement in remote cardiovascular disease monitoring systems.

Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture

In this paper, we proposed a novel Coordinate Rotation Digital Computer (CORDIC) rotator algorithm that converges to the final target angle by adaptively executing appropriate iteration steps while keeping the scale factor virtually constant and completely predictable. The new feature of our scheme is that, depending on the input angle, the scale factor can assume only two values, viz., 1 and 1//spl radic/2, and it is independent of the number of executed iterations, nature of iterations, and word length. In this algorithm, compared to the conventional CORDIC, a reduction of 50% iteration is achieved on an average without compromising the accuracy. The adaptive selection of the appropriate iteration step is predicted from the binary representation of the target angle, and no further arithmetic computation in the angle approximation datapath is required. The convergence range of the proposed CORDIC rotator is spanned over the entire coordinate space. The new CORDIC rotator requires 22% less adders and 53% less registers compared to that of the conventional CORDIC. The synthesized cell area of the proposed CORDIC rotator core is 0.7 mm/sup 2/ and its power dissipation is 7 mW in IHP in-house 0.25-/spl mu/m BiCMOS technology.

On the single-chip implementation of a Hiperlan/2 and IEEE 802.11a capable modem

Broadband wireless communication is the key technology to a new generation of products in the consumer market. The emerging standards for the 5 GHz band will form the basis for many applications requiring a high communication bandwidth. Low cost and low power dissipation will be a prerequisite for most mobile applications. One way to realize low-cost systems is to reduce the system complexity and deploy highly integrated components. The work presented in this article discusses aspects of implementing a complete Hiperlan/2 and IEEE 802.11a compliant modem, including the physical layer as well as the data link control layer, into a single chip.

A VLSI array architecture for realization of DFT, DHT, DCT and DST

A unified array architecture is described for computation of DFT, DHT, DCT and DST using a modified CORDIC (CoOrdinate Rotation DIgital Computer) arithmetic unit as the basic Processing Element (PE). All these four transforms can be computed by simple rearrangement of input samples. Compared to five other existing architectures, this one has the advantage in speed in terms of latency and throughput. Moreover, the simple local neighborhood interprocessor connections make it convenient for VLSI implementation. The architecture can be extended to compute transformation of longer length by judicially cascading the modules of shorter transformation length which will be suitable for Wafer Scale Integration (WSI). CORDIC is designed using Transmission Gate Logic (TGL) on sea of gates semicustom environment. Simulation results show that this architecture may be a suitable candidate for low power/low voltage applications.

On the application of quantitative EEG for characterizing autistic brain: a systematic review

Autism-Spectrum Disorders (ASD) are thought to be associated with abnormalities in neural connectivity at both the global and local levels. Quantitative electroencephalography (QEEG) is a non-invasive technique that allows a highly precise measurement of brain function and connectivity. This review encompasses the key findings of QEEG application in subjects with ASD, in order to assess the relevance of this approach in characterizing brain function and clustering phenotypes. QEEG studies evaluating both the spontaneous brain activity and brain signals under controlled experimental stimuli were examined. Despite conflicting results, literature analysis suggests that QEEG features are sensitive to modification in neuronal regulation dysfunction which characterize autistic brain. QEEG may therefore help in detecting regions of altered brain function and connectivity abnormalities, in linking behavior with brain activity, and subgrouping affected individuals within the wide heterogeneity of ASD. The use of advanced techniques for the increase of the specificity and of spatial localization could allow finding distinctive patterns of QEEG abnormalities in ASD subjects, paving the way for the development of tailored intervention strategies.

Modeling SWCNT Bandgap and Effective Mass Variation Using a Monte Carlo Approach

Synthesizing single-walled carbon nanotubes (SWCNTs) with accurate structural control has been widely acknowledged as an exceedingly complex task culminating in the realization of CNT devices with uncertain electronic behavior. In this paper, we apply a statistical approach in predicting the SWCNT bandgap and effective mass variation for typical uncertainties associated with the geometrical structure. This is first carried out by proposing a simulation-efficient analytical model that evaluates the bandgap (Eg) of an isolated SWCNT with a specified diameter (d) and chirality (¿). Similarly, we develop an SWCNT effective mass model, which is applicable to CNTs of any chirality and diameters >1 nm. A Monte Carlo method is later adopted to simulate the bandgap and effective mass variation for a selection of structural parameter distributions. As a result, we establish analytical expressions that separately specify the bandgap and effective mass variability (Eg¿, m¿ *) with respect to the CNT mean diameter (d¿) and standard deviation (d¿). These expressions offer insight from a theoretical perspective on the optimization of diameter-related process parameters with the aim of suppressing bandgap and effective mass variation.

A Time-Domain Morphology and Gradient based algorithm for ECG feature extraction

A Time Domain Morphology and Gradient (TDMG) based algorithm is presented in this paper for the extraction of all the fiducial time instances from a single PQRST complex. By estimating these characteristic points, all clinically important temporal ECG parameters can be calculated. The proposed algorithm is based on a combination of extrema detection and slope information, with the use of adaptive thresholding to achieve the extraction of 11 time instances. A pre-processing step removes any noise and artefacts from the captured ECG signal. Initially, the position of the R-wave and the QRS-complex boundaries are localized in time. Following, by focusing on the part of the signal that precedes and succeeds the QRS-complex, the remaining fiducial points from the P and T waves are estimated. The initial localisation of the wave boundaries is complimented by amendment steps which are introduced to cater for atypical wave morphologies, indicative of particular heart conditions. The proposed algorithm is evaluated on the QT and PTB databases against medically annotated ECG samples. The results demonstrate the ability of the proposed scheme, to estimate the ECG fiducial points with acceptable accuracy from a single-lead ECG signal. In addition, this investigation reveals the ability of the TDMG algorithm to perform accurately irrespective of the lead chosen, the different disease categories and the sampling frequency of the captured ECG signal.

Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems

In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and their implementation. Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arc tangent computation unit, numerically controlled oscillator, and the decimation filters. The use of multiple clock domains and clock gating reduces the power consumption further. These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25mum- 5-metal layer BiCMOS technology from Institute for High Performance Microelectronics.