Alfred L. Crouch

Testability features of the MC68060 microprocessor

This report describes the testability design goals, constraints, and strategies used in the development of the MC68060 microprocessor. It explores the design choices that were made and the considerations that led to those choices. It presents the architectures and methodologies used to implement the design choices, and ends by describing the successes, failures, and future refinements of the test methodologies and architectures.

The testability features of the 3rd generation ColdFire/sup (R)/ family of microprocessors

A description of the DFT and test challenges faced, and the solutions applied, to the newest member of the ColdFire/sup (R)/ microprocessor family, the MCF5307, is described. The MCF5307 is the first member of the family to have on-chip, PLL-sourced, dual clock domains where the bus interface and the internal core microprocessor operate at different, but selectable, frequency ratios; and the internal microprocessor core of the MCF5307 was designed as a separate stand-alone core that contained multiple embedded memory arrays. The DFT challenges and solutions described involve the development of the at-speed AC scan test architecture and scan vectors in a multiple clock domain environment; the application of memory BIST to multiple embedded memories in a cost effective manner; and the handling of an on-chip PLL clock source.

A case study of the test development for the 2nd generation ColdFire/sup R/ microprocessors

A case study of the development of the design for test methodology of the second generation of the ColdFire/sup R/ Microprocessor Family is described from the viewpoint of goals, initial strategy and implementation. Methodology includes at-speed scan path design, path delay testing, I/sub DDQ/ and direct access test modes for embedded memories. Scan tests are applied with timing identical to that specified for peak performance normal operation.

Low power mode and IEEE 1149.1 compliance: a low power solution

The requirements of a low power mode, built into complex VLSI ICs such as microprocessors, seem to conflict with the IEEE 1149.1 Standard (JTAG). The perception that the TAP Pins-T~R~S~T~, TMS, and TDI-must be equipped with power-consuming pullup resistors or that low power and 1149.1 modes of operation are mutually exclusive is erroneous. Certain techniques can be used during the design and implementation of the TAP and the TAP controller that will allow the IC to enter low power mode without interference or unnecessary power consumption from the JTAG logic and will allow JTAG operations during low power mode while maintaining full compliance to the 1149.1 standard.

FPGA-Based Embedded Tester with a P1687 Command, Control, and Observe-System

This article discusses the embedding of a tester on an FPGA, which uses IJTAG to enable flexible and dynamic access to test configurations of the on-chip instruments.

Test development for second-generation ColdFire microprocessors

This case study shows how test designers met fundamental microprocessor testing goals while adapting existing methodologies to a new architecture.

Test development for a third-version ColdFire microprocessor

The design-for-test methodology of the MCF5307 device is described, illustrating issues faced, how solutions were derived, and results.

Position Statement: The DFT Trip -- Dad Are We There Yet?

When I started as a design-for-test (DFT) engineer many, many, many, years ago, I had to crawl through schematics and find places to insert controllability and observability into systems, boards, and chips to make them more testable. Latchback, Testpoint Insertion, and SCOAP analysis were fundamental weapons in the test war. The goal was to place hooks in the design to help with debug and diagnostics and to meet customer defined quality levels. As a matter of fact, there was more emphasis in being able to detect and isolate to the failed element after the system was put in use, than using the DFT to assist with production test.