Grady Giles

Test Access Mechanism for Multiple Identical Cores

A new test access mechanism (TAM) for multiple identical embedded cores is proposed. It exploits the identical nature of the cores and modular pipelined circuitry to provide scalable and flexible capabilities to make tradeoffs between test time and diagnosis over the manufacturing maturity cycle from low-yield initial production to high-yield, high-volume production. The test throughput gains of various configurations of this TAM are analyzed. Forward and reverse protocol translations for core patterns applied with this TAM are described.

The Test Features of the Quad-Core AMD Opteron- Microprocessor

This paper describes the design-for-test (DFT) features of the quad-core AMD-OpteronTM microprocessor.

EDT bandwidth management - Practical scenarios for large SoC designs

The paper discusses practical issues involved in applying scan bandwidth management to large industrial system-on-chip (SoC) designs deploying embedded test data compression. These designs pose significant challenges to the channel bandwidth management methodology itself, flow, and tools. The paper introduces several test logic architectures that facilitate preemptive test scheduling for SoC circuits with EDT-based test data compression. Moreover, some recently proposed SoC test scheduling algorithms are refined accordingly by making provision for (1) setting up test configurations minimizing test time, (2) optimization of SoC pin allocation based on scan data volume, and (3) handling physical constraints in realistic applications. Detailed presentation of a case study is illustrated with a variety of experiments that allow one to learn how to tradeoff different architectures and test scheduling.

Test Access Mechanism in the Quad-Core AMD Opteron Microprocessor

Multicore microprocessors provide a natural application environment for IEEE Std 1500 and, as this article proves, allow for innovative approaches that capitalize on the fact that the various cores are identical.

The scan-DFT features of AMD's next-generation microprocessor core

There is an ever-increasing demand for higher performance microprocessors within a given power budget. This demand forces design choices - that were once seen only in high-speed custom blocks - to spread throughout the microprocessor core. These unique design structures, combined with the nanometer technology test challenges such as crosstalk, process variations, power-supply noise, and resistive short and open defects, lead to unique test challenges for todays high-performance microprocessor core. In this paper, we present the scan architecture-related design-for-test (DFT) features and corresponding verification strategies of the nextgeneration Advanced Micro Devices (AMD) high-performance microprocessor core.

Is scan (alone) sufficient to test today's microprocessors? Not quite, but we can't get the job done without it

The question really comes back to the sufficiency of the quality provided by scan patterns on todays microprocessors. State-of-the-art microprocessor designs and manufacturing processes are always pushing the envelope. This aggressive posture with respect to the underlying technology is one cause of the demise of the stuck-at fault model and its cousins. ATPG is only as good as its fault model. Scan has less utility for testing some of the very analog features of todays microprocessors such as gigabyte/sec differential busses. Though scan has been used in the past for I/O timing spec and speed bin testing, this is less applicable than it once was because the silicon is so much faster than the ATE. I recommend using best at-speed scan, ATPG, and BIST practices to achieve quantifiably high fault coverage, and also performing functional sequences under stress conditions.

Structural test of power-only defects: ATPG or ad-hoc?

Power-only defects do not cause logical failures in a chip but induce more power consumption. For battery-driven semiconductor chips and others with military-level quality requirements, power-only defects have to be screened out during manufacturing test. To reduce the associated test cost, structural test of those defects is a must. With a dedicated example, this paper demonstrates two methods to structurally detect such defects, i.e., testing them along with regular ATPG vectors and creating a special test mode for detection. This paper also compares the two proposals based on different tradeoff requirements. Finally, it summarizes general criteria for selecting structural test methods for detecting those power-only defects.

Power faults - What is our tolerance for defects?

Modern ICs have power-saving features that are actuated by logic but may or may not be observed in logic. How much power savings loss does a defect in the circuitry of such a power saving feature have to cause before we regard the chip as defective?

At-speed scan tests are a reality (and a necessity)

Some defects in todays vanishingly tiny IC process geometries are manifested as delay faults which are best detected by test patterns that contain launch and capture events applied at-speed. While functional tests may meet this criterion, creation of functional tests for specifically targeted delay faults is very problematic. There is no general systematic method to create sufficiently comprehensive functional patterns on a realistic schedule such that project completion is assured by a specific date. A far more reliable strategy is to use scan-based delay tests. AMD is ever more heavily invested in scan-based methods. We have a very capable at-speed scan architecture that we use to test the great majority of the logic circuitry that operates synchronously at GHz frequencies.