Alfredo Rosado Muñoz

FPGA-based embedded Logic Controllers

In general case, reconfigurable logic controllers (RLC) are included into reactive digital embedded systems, carrying out control for several processes proceeding concurrently. The paper presents a practical application of a formal, rule-based specification language in Gentzen sequent logic, which is used as an intermediate textual description of a control interpreted Petri net. On the other hand exactly the same description serves also as logic design expressions, related with different versions of functionally equivalent concurrent state machine models, considered on Register Transfer Level. The symbolic rule-based specification of Petri net-based embedded Logic Controllers (LCs) can be step-by step formally transformed into the final specification of concurrent state machine model, closely related with VHDL description, suitable for a direct mapping in reconfigurable logic devices. In this paper it is proposed novel compact form of logic descriptions, directly based on event-oriented specification, where it is assumed that macrocells can be implicitly formed by synthesis tool as containing virtual T flip-flops.

Statechart-based design controllers for FPGA partial reconfiguration

Statechart diagram and UML technique can be a vital part of early conceptual modeling. At the present time there is no much support in hardware design methodologies for reconfiguration features of reprogrammable devices. Authors try to bridge the gap between imprecise UML model and formal HDL description. The key concept in authors proposal is to describe the behavior of the digital controller by statechart diagrams and to map some parts of the behavior into reprogrammable logic by means of group of states which forms sequential automaton. The whole process is illustrated by the example with experimental results.

Remote, web-based laboratory for Programmable Logic Devices

Abstract This work proposes a web-based laboratory for remotely testing FPGA programs on an evaluation board. Using a web browser, the user can download a device configuration file (previously generated with the FPGA commercial tool) and test it in a real FPGA board located in a remote laboratory at the University facilities. The user can control inputs and check outputs’ state. This preliminary study tries to evaluate the possibilities that can be offered to the user, and the restrictions that might apply. Additionally, it describes the proposed infrastructure (hardware and software) needed to successfully deal with all the interesting features that a remote lab system for programmable logic devices should incorporate for learning purposes.

Selection of the Optimal Algorithm for Real-Time Estimation of Beta Band Power during DBS Surgeries in Patients with Parkinson’s Disease

Deep Brain Stimulation (DBS) is a surgical procedure for the treatment of motor disorders in patients with Parkinsons Disease (PD). DBS involves the application of controlled electrical stimuli to a given brain structure. The implantation of the electrodes for DBS is performed by a minimally invasive stereotactic surgery where neuroimaging and microelectrode recordings (MER) are used to locate the target brain structure. The Subthalamic Nucleus (STN) is often chosen for the implantation of stimulation electrodes in DBS therapy. During the surgery, an intraoperative validation is performed to locate the dorsolateral region of STN. Patients with PD reveal a high power in the β band (frequencies between 13 Hz and 35 Hz) in MER signal, mainly in the dorsolateral region of STN. In this work, different power spectrum density methods were analyzed with the aim of selecting one that minimizes the calculation time to be used in real time during DBS surgery. In particular, the results of three nonparametric and one parametric methods were compared, each with different sets of parameters. It was concluded that the optimum method to perform the real-time spectral estimation of beta band from MER signal is Welch with Hamming windows of 1.5 seconds and 50% overlap.