Ali Chamas Al Ghouwayel

Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm

This paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on a reduced-complexity version of the Extended Min-Sum algorithm. The main contributions of this work correspond to the variable node processing, the codeword decision and the elementary check node processing. Post-synthesis area results show that the decoder area is less than 20% of a Virtex 4 FPGA for a decoding throughput of 2.95 Mbps. The implemented decoder presents performance at less than 0.7 dB from the Belief Propagation algorithm for different code lengths and rates. Moreover, the proposed architecture can be easily adapted to decode very high Galois Field orders, such as GF(4096) or higher, by slightly modifying a marginal part of the design.

FPGA implementation of a re-configurable FFT for multi-standard systems in software radio context

This study is focused on the Field Programmable Gate Array (FPGA) implementation of a re-configurable Fast Fourier Transform (FFT) operator able to provide Fourier transforms both over complex infinite field X and Galois finite Field GF. This new re-configurable FFT exploits to a great advantage the possibility to share hardware resources when considering multi-standard scenarios for software radio systems. A re-configurable FFT of length N = 256 has been implemented on FPGA. It achieves a performance-to-cost ratio gain from 24% to 9.4% compared to the basic duplicated solution for which no re-configuration is considered. The proposed technology is strongly connected to further consumer handheld devices such as mobile phones intended to support several standards (digital television, mobile communications, wireless local area network etc) where FFT is involved.

A Systolic LLR Generation Architecture for Non-Binary LDPC Decoders

Non-Binary LDPC codes offer higher performances than their binary counterpart but suffer from higher decoding complexity. A solution to reduce the decoding complexity is to use the Extended Min-Sum algorithm. The first step of this algorithm requires the generation of the first n_m largest Log-Likelihood Ratio (LLR), sorted in increasing order, of each received symbol. In the case where GF(q) symbols are transmitted using a BPSK modulation, we propose a simple systolic architecture that generates the sorted list of symbols.

A Novel Architecture For Elementary Check Node Processing In Non-Binary LDPC Decoders

This brief presents an efficient architecture design for elementary-check-node processing in nonbinary low-density parity-check decoders based on the extended min-sum algorithm. This architecture relies on a simplified version of the bubble check algorithm and is implemented by the means of first-in–first-out. The adoption of this new design at the check node level results in a high-rate low-cost full-pipelined processor. A proof-of-concept implementation of this processor shows that the proposed architecture halves the occupied the field-programmable gate array (FPGA) surface and doubles the maximum frequency without modifying the input/output behavior of the previous one.

On the FPGA implementation of the Fourier Transform over finite fields GF(2m)

The hardware design and implementation of cyclotomic Fast Fourier Transform (FFT) over finite fields GF(2m) is described. By reformulating the algorithm presented in [8], we introduce a hardware interpretation to design a highly parallel and parameterized architecture of the cyclotomic FFT. Based on four stages and modular structure of last stage, this architecture can operate at different throughput rates. Compared to another implemented algorithm [9] which operates at fc (the system clock frequency), the proposed architecture allows to reach a very high throughput rate which, for 256-point FFT, can get hold of 8.5 fc. An FPGA implementation of the proposed architecture is given where the critical path delay and the hardware complexity are evaluated.

Pre-Sorted Forward-Backward NB-LDPC Check Node Architecture

This paper deals with reduced-complexity NB-LDPC check node implementation based on the Extended Min-Sum algorithm. We propose to apply a recently introduced pre-sorting technique to the forward-backward architecture. The pre-sorting of the check node inputs allows for significant complexity reduction. Simulation and synthesis results showed that this approach does not introduce any performance loss and can lead to significant area reduction in FPGA implementations (up to 54% for high check node degrees).

An efficient algorithm for automatic recognition of the Lebanese car license plate

In the last decades, the number of vehicles has increased drastically. With this increase, it is becoming difficult to keep track of each vehicle for the purpose of law enforcement and traffic management. Automatic License Plate Recognition is implemented to make human work easier besides it can reduce the uses of human power because of its flexibility and the easy of its implementation. In this paper we propose an efficient algorithm for automatic recognition of any license plate, with an emphasis on the Lebanese license plates where some of their features have been exploited well to reduce the recognition errors. The proposed algorithm has been implemented using the Image Processing Toolbox in MATLAB R2013b (8.2.0.701). Our simulations show that the recognition errors have been reduced well upon exploiting the fact that the Lebanese license plates are written in two formats (Arabic and Hindi). Furthermore, our algorithm has an option to benefit from the presence of the license plates in the front and the rear end of the car to enhance the performance.

Extended-forward architecture for simplified check node processing in NB-LDPC decoders

This paper focuses on low complexity architectures for check node processing in Non-Binary LDPC decoders. To be specific, we focus on Extended Min-Sum decoders and consider the state-of-the-art Forward-Backward and Syndrome-Based approaches. We recall the presorting technique that allows for significant complexity reduction at the Elementary Check Node level. The Extended-Forward architecture is then presented as an original new architecture for efficient syndrome calculation. These advances lead to a new architecture for check node processing with reduced area. As an example, we provide implementation results over GF(64) and code rate 5/6 showing complexity reduction by a factor of up to 2.6.

Modeling and design of NFC/RFID backbone using a Computer Aided Design tool

This paper introduces a Schematic Model of the Magnetic Coupling revolving in the NFC/RFID Systemusing a Computer Aided Design tool. Industry bodies are developing programs to improve NFC/RFID devices based on several specifications. Magnetic coupling is one of the most important factorsin near-field communication. Thus a Schematic Model is proposed, based on a precise standardized specifications and dimensions, which takes into consideration the impedance matching network, in addition to the coupling coefficient and the voltage transformation. Simulations are accomplished using Advanced Design System (ADS) which yields pretty good results that may help designers of the NFC/RFID technology to ameliorate their suggested design for an efficient and reliablecommunication.

Decoding of iterative Non-Binary LDPC codes using a near Maximum Likelihood approach

This paper investigates the decoding of rate 1/2 Non-Binary LDPC codes using a non-iterative approach based on the Maximum-Likelihood (ML) principle. The iterative decoding approach based on the well known Extended-Min-Sum (EMS) algorithm, considered as the most efficient decoding algorithm to decode NB-LDPC codes, executes the decoding process iteratively. The main operations of this algorithm are the variable and check node updates which are performed at least eight times requiring a long decoding time to achieve good performance in terms of Frame Error Rate (FER). The proposed decoding near ML approach is based on ML search where the number of candidates is highly reduced using a technique privileging the most reliable and nearest codewords. Simulation results show that the proposed algorithm achieves, at a reduced list of 5 searched candidates in average at 3 dB, the performance offered by the EMS algorithm. We also show that by slightly increasing the list of candidates, the proposed algorithm outperforms the EMS algorithm.