Hussein Hijazi

Modeling and design of NFC/RFID backbone using a Computer Aided Design tool

This paper introduces a Schematic Model of the Magnetic Coupling revolving in the NFC/RFID Systemusing a Computer Aided Design tool. Industry bodies are developing programs to improve NFC/RFID devices based on several specifications. Magnetic coupling is one of the most important factorsin near-field communication. Thus a Schematic Model is proposed, based on a precise standardized specifications and dimensions, which takes into consideration the impedance matching network, in addition to the coupling coefficient and the voltage transformation. Simulations are accomplished using Advanced Design System (ADS) which yields pretty good results that may help designers of the NFC/RFID technology to ameliorate their suggested design for an efficient and reliablecommunication.

Decoding of iterative Non-Binary LDPC codes using a near Maximum Likelihood approach

This paper investigates the decoding of rate 1/2 Non-Binary LDPC codes using a non-iterative approach based on the Maximum-Likelihood (ML) principle. The iterative decoding approach based on the well known Extended-Min-Sum (EMS) algorithm, considered as the most efficient decoding algorithm to decode NB-LDPC codes, executes the decoding process iteratively. The main operations of this algorithm are the variable and check node updates which are performed at least eight times requiring a long decoding time to achieve good performance in terms of Frame Error Rate (FER). The proposed decoding near ML approach is based on ML search where the number of candidates is highly reduced using a technique privileging the most reliable and nearest codewords. Simulation results show that the proposed algorithm achieves, at a reduced list of 5 searched candidates in average at 3 dB, the performance offered by the EMS algorithm. We also show that by slightly increasing the list of candidates, the proposed algorithm outperforms the EMS algorithm.

Simplified representation of the LLR messages in the check node processor for NB-LDPC decoder

Non-Binary Low Density Parity Check Codes (NB-LDPC) are nowadays considered as a potential competitor of both binary LDPC and convolutional Turbo Codes, mainly when codes with short and moderate codeword lengths are used. The decoding process of these codes suffers from a high computational complexity which necessitates a high memory requirements to store the intrinsic and extrinsic Likelihood Ratio (LLR) messages. This paper addresses a simplified and efficient coding technique of the binary words carrying the LLR values by storing the difference of two consecutive LLRs instead of the entire values in the Check Node (CN) processor of NB-LDPC Decoder. A combined approach mixing two techniques: partial truncation and 2-bit coding technique leading to a memory reduction of 38 % is also presented. The Monte Carlo simulation results show that the proposed LLR representation schemes do not introduce a significant performance loss of the code.