Ali El-Zein

Verification of Galois field based circuits by formal reasoning based on computational algebraic geometry

Algebraic error correcting codes (ECC) are widely used to implement reliability features in modern servers and systems and pose a formidable verification challenge. We present a novel methodology and techniques for provably correct design of ECC logics. The methodology is comprised of a design specification method that directly exposes the ECC algorithm’s underlying math to a verification layer, encapsulated in a tool “BLUEVERI”, which establishes the correctness of the design conclusively by using an apparatus of computational algebraic geometry (Buchberger’s algorithm for Gröbner basis construction). We present results from its application to example circuits to demonstrate the effectiveness of the approach. The methodology has been successfully applied to prove correctness of large error correcting circuits on IBM’s POWER systems to protect memory storage and processor to memory communication, as well as a host of smaller error correcting circuits.

Simulating nonuniform lossy lines with frequency dependent parameters by the method of characteristics

A method of characteristics solution of a nonuniform transmission line having frequency-dependent per-unit-length parameters is formulated. The method, in general, requires the use of FFT to incorporate the frequency-dependent components of the distributed parameters in the time-domain equations. For skin-effect frequency-dependence, an analytical technique to avoid the use of FFT is presented. Also, a formula for estimating the discretization error is given.<<ETX>>

Separation of concerns for hardware components of embedded systems in BIP

Memory-based concerns such as Design-for-test, logic built in self test, memory technology mapping and clock division concerns traditionally happen at circuit-level and require team-months of verification time. We present a novel hardware concern-based methodology for embedded system frameworks that enables automatic separation of memory based hardware concerns at high-level where verification is easier. The methodology relies on a conservative memory inference transformation that separates sequential from combinational elements. We developed a tool that automatically performs the transformation for BIP, an open source embedded systems design framework. It takes entry BIP model code and outputs BIP model code where memory elements are separated from the rest of the logic. We evaluated our method with three BIP case studies. Our results show that our method enabled designers to identify and fix injected defects at the BIP level, where they are more comfortable, in reasonable time without the need to dive into the circuitry that is highly coupled with concerns.