Alexey Lvov

ScaffCC: a framework for compilation and analysis of quantum computing programs

Quantum computing is a promising technology for high-performance computation, but requires mature toolflows that can map large-scale quantum programs onto targeted hardware. In this paper, we present a scalable compiler for large-scale quantum applications, and show the opportunities for reducing compilation and analysis time, as well as output code size. We discuss the similarities and differences between compiling for a quantum computer as opposed to a classical computer, and present a state-of-the-art approach for compilation of classical circuits into quantum circuits. Our work also highlights the importance of high-level quantum compilation for logical circuit translation, quantitative analysis of algorithms, and optimization of circuit lengths.

ScaffCC: Scalable compilation and analysis of quantum programs

We present ScaffCC, a scalable compilation and analysis framework based on LLVM, which can be used for compiling quantum computing applications at the logical level. Drawing upon mature compiler technologies, we discuss similarities and differences between compilation of classical and quantum programs, and adapt our methods to optimizing the compilation time and output for the quantum case. Our work also integrates a reversible-logic synthesis tool in the compiler to facilitate coding of quantum circuits. Lastly, we present some useful quantum program analysis scenarios and discuss their implications, specifically with an elaborate discussion of timing analysis for critical path estimation. Our work focuses on bridging the gap between high-level quantum algorithm specifi- cations and low-level physical implementations, while providing good scalability to larger and more interesting problems

The problem of optimal placement of sub-resolution assist features (SRAF)

In this paper, we present a formulation of the Sub-Resolution Assist Feature (SRAF) placement problem as a geometric optimization problem. We present three independent geometric methodologies that use the above formulation to optimize SRAF placements under mask and lithographic process constraints. Traditional rules-based methodology, are mainly one dimensional in nature. These methods, though apparently very simple, has proven to be inadequate for complex two-dimensional layouts. The methodologies presented in this paper, on the other hand, are inherently two-dimensional and attempt to maximize SRAF coverage on real and complex designs, and minimizes mask rule and lithographic violations.

Novel algorithms for placement of rectangular covers for mask inspection in advanced lithography and other VLSI design applications

The continuous drive of very large scale integrated (VLSI) chip manufacturers to meet Moores law has spurred the development of novel resolution enhancement techniques (RETs) and optical proximity correction (OPC) methodologies in optical microlithography. These RET and OPC methods have increased the complexity of mask-manufacturing manifold and have, at the same time, put added emphasis on the mask inspection procedure. A technique to simplify mask inspection is to identify rectangular regions on the mask that do not require inspection. Such a region is referred to as a do not inspect region (DNIR). A novel and practical algorithm to place DNIR rectangles on the mask is presented. It is shown that the most general DNIR placement problem is at least NP-Hard (Garey and Johnson, 1979). However, under certain relaxed criteria, there exists a polynomial-time algorithm for DNIR placement using dynamic programming. However, the optimal algorithm has very-high-degree polynomial bounds on its runtime and space complexities. On the other hand, a very simple greedy algorithm extended by lookahead and randomization, or by simulated annealing, can greatly improve the performance of the DNIR placement and produce near-optimal results. Although the algorithm developed in this work is targeted primarily toward DNIR placement, it has many other VLSI design applications.

Verification of Galois field based circuits by formal reasoning based on computational algebraic geometry

Algebraic error correcting codes (ECC) are widely used to implement reliability features in modern servers and systems and pose a formidable verification challenge. We present a novel methodology and techniques for provably correct design of ECC logics. The methodology is comprised of a design specification method that directly exposes the ECC algorithm’s underlying math to a verification layer, encapsulated in a tool “BLUEVERI”, which establishes the correctness of the design conclusively by using an apparatus of computational algebraic geometry (Buchberger’s algorithm for Gröbner basis construction). We present results from its application to example circuits to demonstrate the effectiveness of the approach. The methodology has been successfully applied to prove correctness of large error correcting circuits on IBM’s POWER systems to protect memory storage and processor to memory communication, as well as a host of smaller error correcting circuits.

On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques

The continued delay of higher resolution alternatives for lithography, such as EUV, is forcing the continued adoption of multi-patterning solutions in new technology nodes, which include triple and quadruple patterning using several lithography-etch steps. In the design space each pattern of a multi-patterning solution is modeled as a color on a shape. Designers or EDA tools must determine the colors that each shape is assigned so that the relative position of any two shapes of the same color does not violate the design rules. This results in a shapes layout coloring problem which is formulated as the traditional k-coloring problem in a graph. Because color interactions cross cell boundaries, coloring of a flat (as opposed to hierarchical) design becomes necessary, tremendously increasing the size of the input graph. If a color conflict occurs, any attempt to fix it may cause a chain reaction propagating through the whole design space which makes any approach of the type color_greedily - fix_conflicts - loop_back infeasible. Given the situation, it is extremely desirable to have a set of design rules which provably guarantee k-colorability and admit a practical coloring algorithm. In this paper we formulate such sets of design rules for triple and quadruple patterning problems. For these sets of rules we provide proofs of colorability along with the coloring algorithms with the runtime upper bound of O(n·log n). We also show that our sets of design rules are almost tight in the sense that even a very small relaxation of the formulated rules leads to existence of not k-colorable designs.

Floorplanning challenges in early chip planning

Early chip planning is becoming more critical as server system designers strive to explore a large design space with multiple cores and accelerators in an advanced silicon technology that includes 3D chip stacking. During early chip planning, designers search for the high-level design and layout that best satisfies a myriad of constraints and targets. In this paper, we discuss our experience in applying traditional floorplanning tools at this early stage and suggest how they might be adapted for early floorplanning.