Ali Nikoofard

Analysis of imperfections in N-phase high-Q band-pass filters

The effect of clock skew and duty-cycle on the performance of high-Q N-phase band-pass filters (BPFs) have been examined in this paper. Following a mathematical approach and using the analytical derivations carried out, the effects of such non-idealities as clock skew and duty-cycle error are determined in an N-path filter. It is analytically proved that image signals from all integer multiples of the clock signal, rather than just those at (1 ± kN) multiples of the clock signal, land atop the wanted RF spectrum. In a real world clock generator, with non-idealities in effect, filtering property and proper behavior of the filter is adversely affected. Finally, system level simulation along with circuit simulation using TSMC 0.18μm process have been performed which corroborate the proposed analytical derivations.

Phase calibration in mutual injection-pulled quadrature oscillators

An alternative approach to analysis, design and implementation of injection-locked quadrature oscillators is proposed in this paper. A novel technique is presented which allows the effects of the mismatches due to imbalances in the I/Q paths in transceivers (TRX) to be mitigated, and hence the orthogonality of the these vectors be maintained. This technique alleviates the effects of imbalances in a transceiver between I/Q paths, which would otherwise pose many threats to the performance of the system, namely image rejection ratio (IRR) degradation, gain reduction in mixers, desensitization of the RX, and ect. As a design example, a CMOS quadrature oscillator (QOSC) at the frequency of 3.5GHz has been designed and simulated using TSMC 0.18μm technology. Monte-Carlo simulations have also been performed which indicate that the design is robust to unwanted PVT variations.

Low-complexity N-port ADCs using 2-D Δ-Σ noise-shaping for N-element array receivers

A novel multi-dimensional noise-shaping method is proposed to extend Δ-Σ modulation to the two-dimensional (2-D) (space, time) case. It uses spatial oversampling to provide another degree of freedom for ADC designers to shape quantization noise when temporal oversampling is limited. The method uses lossless discrete integrators (LDIs) to implement spatial integrators and is suitable for use in microwave and mm-wave array processing systems. The resulting 2-D noise shaping reduces the spectral overlap of a desired array signal with that of quantization noise. Shaped noise can then be removed from the region of support (ROS) of the array signal using 2-D filtering, thus improving the overall signal-to-quantization noise ratio (SQNR) and effective number of bits (ENOB). Simulation results from an integrated 64-channel converter in UMC 65nm CMOS prove the functionality of the approach. Experimental results from a board-level 64-channel converter are also presented.

An 11.5 nW broadband wake-up RF receiver with −60 dBm sensitivity at 50 MHz

We present an ultra-low-power broadband wakeup RF receiver (WUR) for autonomous wireless sensor nodes (WSNs). Decreasing static power consumption of the WUR is critical for increasing the operational lifetime of the node. Several techniques are introduced to minimize power consumption while maintainin sensitivity, including step-up impedance transformation, an ultra-low-power RF amplifier, and digital offset adjustment. RF energy harvesting using a rectifier is also proposed to increase node lifetime. The receiver is designed and simulated using UMC 65 nm CMOS and has a power consumption of 11.5 nW. It successfully demodulates 1 kbps on-off-keyed data from a −60 dBm carrier at 50 MHz with an impedance of 1.8 kΩ across the input terminals of the RF receiver. This work surpasses state-of-the-art WURs in terms of sensitivity-power trade-off.

Analysis of the effects of clock imperfections in N-path filters

In this paper, the effect of imperfections on the behavior of N-path filters is investigated. Exact mathematical derivations are presented which describe the effect of clock skew and finite fall/rise time on the impedance transformation behavior of N-path filters. In the ideal case, the N-path filter is supposed to provide a short-circuit to the ground for undesired frequency contents and an open-circuit for the desired signal so that it lies within the passband of the filter. It is shown that clock skew and finite clock fall/rise time result in a non-zero impedance for frequency contents other than the clock frequency and a smaller impedance for the desired voltage. In a real circuit with these effects present, the performance and filtering characteristics of the filter are altered. Finally, a technique has been introduced by means of which a specific harmonic fold-back component can be canceled by proper choice of clock timing.

A fully analog side-band cancellation technique in radio-frequency transmitters

In this paper, a new fully analog technique is proposed by means of which the adverse effects of frequency dependent gain/phase errors in quadrature transmitters are suppressed. Two separate phase and gain mismatch cancellation loops are implemented which search for the minimum side-band component. A new sign detection method is also introduced which makes sure the direction of the loop is correct. Analytical models and mathematical derivations have been presented which corroborates the circuit implementation. A proof of concept prototype using off-the-shelf components have also been measured which suggests 38-dB side-band rejection (SBR). Furthermore, the measured TX EVM and BER are improved by an order of magnitude for a QPSK-modulated input signal.

Off-Resonance Oscillation, Phase Retention, and Orthogonality Modeling in Quadrature Oscillators

Two important drawbacks of parallel coupled LC quadrature oscillators (P-QOSC) which have not heretofore been addressed thoroughly in the literature are obviated simultaneously in this paper. The first, has to do with the inevitable off-tune operation of the tank which results in quality factor (Q) degradation, and hence, phase noise deterioration. The other, stems from process, voltage, and temperature (PVT) variations which exacerbate quadrature accuracy. Here, a feedback loop is presented which generates a control signal by mixing the quadrature outputs and tunes the injection strength in the coupled oscillators autonomously. A complex coupling factor is implemented which compensates the phase error to prohibit phase noise degradation. The operation of proposed loop is comprehensively studied mathematically. Measurement results of a 0.18 μm CMOS prototype with an active area of 0.5 mm2 and an overall power consumption of 5 mW corroborate the functionality of the proposed method. Finally, experimental results prove FoM of 185 dB for the core oscillator and a quadrature phase error of less than 0.8°.

Zero-power mismatch-independent Digital to Analog converter

A new switched-capacitor Digital to Analog converter (DAC) is presented. In this method, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch and process independent by virtue of the correction phase. That is after some correction phases, the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply.