Arjuna Madanayake

Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions

Video processing systems such as HEVC requiring low energy consumption needed for the multimedia market has lead to extensive development in fast algorithms for the efficient approximation of 2-D DCT transforms. The DCT is employed in a multitude of compression standards due to its remarkable energy compaction properties. Multiplier-free approximate DCT transforms have been proposed that offer superior compression performance at very low circuit complexity. Such approximations can be realized in digital VLSI hardware using additions and subtractions only, leading to significant reductions in chip area and power consumption compared to conventional DCTs and integer transforms. In this paper, we introduce a novel 8-point DCT approximation that requires only 14 addition operations and no multiplications. The proposed transform possesses low computational complexity and is compared to state-of-the-art DCT approximations in terms of both algorithm complexity and peak signal-to-noise ratio. The proposed DCT approximation is a candidate for reconfigurable video standards such as HEVC. The proposed transform and several other DCT approximations are mapped to systolic-array digital architectures and physically realized as digital prototype circuits using FPGA technology and mapped to 45 nm CMOS technology.

Multiplier-free DCT approximations for RF multi-beam digital aperture-array space imaging and directional sensing

Multi-beamforming is an important requirement for broadband space imaging applications based on dense aperture arrays (AAs). Usually, the discrete Fourier transform is the transform of choice for AA electromagnetic imaging. Here, the discrete cosine transform (DCT) is proposed as an alternative, enabling the use of emerging fast algorithms that offer greatly reduced complexity in digital arithmetic circuits. We propose two novel high-speed digital architectures for recently proposed fast algorithms (Bouguezel, Ahmad and Swamy 2008 Electron. Lett. 44 1249?50) (BAS-2008) and (Cintra and Bayer 2011 IEEE Signal Process. Lett. 18 579?82) (CB-2011) that provide good approximations to the DCT at zero multiplicative complexity. Further, we propose a novel DCT approximation having zero multiplicative complexity that is shown to be better for multi-beamforming AAs when compared to BAS-2008 and CB-2011. The far-field array pattern of ideal DCT, BAS-2008, CB-2011 and proposed approximation are investigated with error analysis. Extensive hardware realizations, implementation details and performance metrics are provided for synchronous field programmable gate array (FPGA) technology from Xilinx. The resource consumption and speed metrics of BAS-2008, CB-2011 and the proposed approximation are investigated as functions of system word size. The 8-bit versions are mapped to emerging asynchronous FPGAs leading to significantly increased real-time throughput with clock rates at up to 925.6?MHz implying the fastest DCT approximations using reconfigurable logic devices in the literature.

Multidimensional (MD) Circuits and Systems for Emerging Applications Including Cognitive Radio, Radio Astronomy, Robot Vision and Imaging

Advances in the performance of VLsi circuits are leading to a number of emerging applications of multidimensional (md) filters. Early progress was focused on the numerical design of two dimensional (2-d) transfer functions and the challenging stability issues associated with low-complexity infinite impulse response (iir) implementations. However, over the last decade or so, important practical advances have occurred in the design of 3-d and 4-d iir filters, leading to some important emerging applications. in this tutorial article, some of these applications are described, with emphasis on 2-d spatio-temporal beamforming and 4-d light field processing. in particular, advances in spatio-temporal beamforming for cognitive radio systems and for synthetic aperture radio telescopes are considered. in the 4-d case, we describe a class of 4-d light field filters for image processing, 4-d hyper-fan filters for low-light imaging, depth filtering, denoising and the attenuation of distracting objects, with applications in computational photography and habitat monitoring. Both analog and digital systolic VLsi circuit implementations are described with emphasis on recent progress using field programmable gate array (fPgA)-based and digital VLsi circuits that can potentially operate at radio frequencies in the multi-gHz range. these new innovations open up exciting possibilities for real-time md filters having frames rates in the multi-gHz for emerging radio frequency (rf) antenna signal processing and imaging systems.

A Row-Parallel 8

An algebraic integer (AI)-based time-multiplexed row-parallel architecture and two final reconstruction step (FRS) algorithms are proposed for the implementation of bivariate AI encoded 2-D discrete cosine transform (DCT). The architecture directly realizes an error-free 2-D DCT without using FRSs between row-column transforms, leading to an 8 × 8 2-D DCT that is entirely free of quantization errors in AI basis. As a result, the user-selectable accuracy for each of the coefficients in the FRS facilitates each of the 64 coefficients to have its precision set independently of others, avoiding the leakage of quantization noise between channels as is the case for published DCT designs. The proposed FRS uses two approaches based on: 1) optimized Dempster-Macleod multipliers, and 2) expansion factor scaling. This architecture enables low-noise high-dynamic range applications in digital video processing that requires full control of the finite-precision computation of the 2-D DCT. The proposed architectures and FRS techniques are experimentally verified and validated using hardware implementations that are physically realized and verified on field-programmable gate array (FPGA) chip. Six designs, for 4-bit and 8-bit input word sizes, using the two proposed FRS schemes, have been designed, simulated, physically implemented, and measured. The maximum clock rate and block rate achieved among 8-bit input designs are 307.787 MHz and 38.47 MHz, respectively, implying a pixel rate of 8 × 307.787≈2.462 GHz if eventually embedded in a real- time video-processing system. The equivalent frame rate is about 1187.35Hz for the image size of 1920 × 1080. All implementations are functional on a Xilinx Virtex-6 XC6VLX240T FPGA device.

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Real-time plane wave (PW) filters find many applications in 2D/3D array signal processing. In this work, FPGA architectures are proposed for the real-time implementation of 2D/3D FIR and IIR PW filters. Fully parallel and time division multiplexed (TDM) FIR/IIR filter structures are described for the implementation of 2D/3D frequency planar and 2D fan filters on Xilinx FPGAs. Simulations demonstrate the usefulness of the FPGA technology for rapidly prototyping real-time VLSI/CMOS implementations of FIR and IIR 2D/3D PW filters. The proposed high-speed parallel 2D IIR filter structures promise temporal band-widths of up to 150 MHz using a 300 MHz FPGA chip and the proposed TDM filter structures may be used to implement 3D beam FPGA filters having a temporal sample rate of 180 KHz for a 40/spl times/40 rectangular sensor array.

8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation

A continuous-time (CT) radio frequency (RF) antenna array beamformer and analog circuit based on a discrete-space-continuous-time (DSCT) 2-D fan-filter having transfer function H_F,A(z_x,s_ct) is derived. The proposed transfer function is based on a 2-D FIR discrete domain fan filter. The discrete domain prototype is converted to the proposed mixed-domain DSCT analog filter by replacing unit sampled delays with CT analog first-order all-pass networks corresponding to the bilinear transform. First-order all-pass network Φ(s_t) is a poor approximation to a CT delay exp(-<i>sT</i>) . To address this, a novel broadband pre-warping method is proposed to exactly compensate for such “bilinear warping”. A 65 nm CMOS VLSI circuit for Φ(<i>s</i>_t) is proposed and an example fan filter with axis oriented at θ₀=35^°, half-fan-angle ε = 5^° and maximum frequency <i>F</i>_u = 2.6 GHz is simulated employing closed-form expressions, an ABCD parameter based model and 65 nm CMOS simulations in Cadence. A stop-band interference rejection of 38 dB is verified by BSIM4 based simulations. The proposed circuit for Φ(<i>s</i>_t) operates at 3.7 mA from a 1.2 V supply. The beamfomer is shown to operate correctly in the presence of PVT variations of Φ(<i>s</i>_t).

FPGA architectures for real-time 2D/3D FIR/IIR plane wave filters

The discrete cosine transform (DCT) is widely employed in image and video coding applications due to its high energy compaction. In addition to 4×4 and 8×8 transforms utilized in earlier video coding standards, the proposed HEVC standard suggests the use of larger transform sizes including 16 × 16 and 32×32 transforms in order to obtain higher coding gains. Further, it also proposes the use of non-square transform sizes as well as the use of the discrete sine transform (DST) in certain intra-prediction modes. The decision on the type of transform used in a given prediction scenario is dynamically made, to obtain required compression rates. This motivated the proposed digital VLSI architecture for a multitransform engine capable of computing 16×16 approximate 2-D DCT/DST transform, with null multiplicative complexity. The relationship between DCT-II and DST-II is employed to compute both transforms using the same digital core, leading to reductions in both area and power. Closed-form relationship between the 16×16 transform and arbitrary smaller sized transform is presented, enabling the usability of this architecture to compute transforms of size 4 · 2P × 4 · 2q where 0 ≤ p, q ≤ 2.

RF Analog Beamforming Fan Filters Using CMOS All-Pass Time Delay Approximations

A time-multiplexed row-parallel architecture is proposed for the real-time implementation of bivariate algebraic integer (AI) encoded 2-D discrete cosine transform (DCT) of images and video sequences. The architecture is based on the Arai algorithm with AI encoding. This leads to an 8×8 2-D DCT which is entirely free of quantization errors. The error free coefficients may be converted into a regular arithmetic format using a final reconstruction step (FRS) at the output stage. The accuracy of the FRS allows each of the 64 coefficients to have its precision set independent of other coefficients without the leakage of quantization noise between coefficient channels. Our architecture leads to low-noise applications in digital video compression, coding, and other image processing applications that rely on the fast systolic computation of the 2-D DCT. A prototype of the 2-D DCT is physically realized, tested, and verified on chip, using a Xilinx Virtex-4 Sx35-10ff668 device. The maximum clock rate was Fclock = 121 MHz, implying an equivalent frame sample rate of 466 Hz, for an image frame size of 1920×1080, which is a common high definition video format.

A multiplication-free digital architecture for 16×16 2-D DCT/DST transform for HEVC

The discrete cosine transform (DCT) is the key step in many image and video coding standards. The eight-point DCT is an important special case, possessing several low-complexity approximations widely investigated. However, the 16-point DCT transform has energy compaction advantages. In this sense, this paper presents a new 16-point DCT approximation with null multiplicative complexity. The proposed transform matrix is orthogonal and contains only zeros and ones. The proposed transform outperforms the well-known Walsh?Hadamard transform and the current state-of-the-art 16-point approximation. A fast algorithm for the proposed transform is also introduced. This fast algorithm is experimentally validated using hardware implementations that are physically realized and verified on a 40?nm CMOS Xilinx Virtex-6 XC6VLX240T FPGA chip for a maximum clock rate of 342?MHz. Rapid prototypes on FPGA for a 8-bit input word size show significant improvement in compressed image quality by up to 1?2?dB at the cost of only eight adders compared to the state-of-art 16-point DCT approximation algorithm in the literature (Bouguezel et al 2010 Proc. 53rd IEEE Int. Midwest Symp. on Circuits and Systems).

Algebraic integer based 8×8 2-D DCT architecture for digital video processing

This letter discusses a wideband inductorless low-noise amplifier (LNA) that incorporates a new active -C element, which draws 170 μA of current. A 10 MHz-2.8 GHz proof-of-concept LNA in 65 nm CMOS is proposed. The LNA itself is power- and noise- matched and achieves noise figures as low as 1 dB, voltage gain of 32 dB and IIP3 of - 13.6 dBm.