Ali Soleimani

FPGA Simulation of Linear and Nonlinear Support Vector Machine

Simple hardware architecture for implementation of pairwise Support Vector Machine (SVM) classifiers on FPGA is presented. Training phase of the SVM is performed offline, and the extracted parameters used to implement testing phase of the SVM on the hardware. In the architecture, vector multiplication operation and classification of pairwise classifiers is designed in parallel and simultaneously. In order to realization, a dataset of Persian handwritten digits in three different classes is used for training and testing of SVM. Graphically simulator, System Generator, has been used to simulate the desired hardware design. Implementation of linear and nonlinear SVM classifier using simple blocks and functions, no limitation in the number of samples, generalized to multiple simultaneous pairwise classifiers, no complexity in hardware design, and simplicity of blocks and functions used in the design are view of the obvious characteristics of this research. According to simulation results, maximum frequency of 202.840 MHz in linear classification, and classification accuracy of 98.67% in nonlinear one has been achieved, which shows outstanding performance of the hardware designed architecture.

Age estimation based on speech features and support vector machine

Age estimation based on humans speech features is an interesting subject in Automatic Speech Recognition (ASR) systems. There are some works in literature on speaker age estimation but it needs more new works especially for Persian speakers. In age estimation, like other speech processing systems, we encounter with two main challenges: finding an appropriate procedure for feature extraction, and selecting a reliable method for pattern classification. In this paper we propose an automatic age estimation system for classification of 6 age groups of various Persian speaker people. Perceptual Linear Predictive (PLP) and Mel-Frequency Cepstral Coefficients (MFCC) are extracted as speech features and SVM is utilized for classification procedure. Furthermore the effects of variations in parameter of kernel function, time of frame length in sampling process, the number of MFCC coefficients, and the order of PLP on system efficiency has been evaluated, and the results has been compared.

Combine particle swarm optimization algorithm and canonical sign digit to design finite impulse response filter

The main contribution of this paper is to design a digital finite impulse response filter using the particle swarm optimization (PSO) algorithm combined canonical signed digit (CSD) representation. The design has been done based on matching certain frequency response and the filter coefficients in CSD representation with limited bits and some of coefficients to be zero, simultaneously. Using CSD representation, multipliers can substitute adders, shifters and subtractors. In filter design, the results show that combining PSO and CSD representations simultaneously is better than combining PSO and CSD sequentially. In addition the results, if the common adders and subtractors were computed for all filter coefficients that specified in CSD representation, significantly reduce the complexity of the hardware implementation of digital FIR filter.

Multibandwidth kernel-based object tracking

Object tracking using Mean Shift (MS) has been attracting considerable attention recently. In this paper, we try to deal with one of its shortcoming. Mean shift is designed to find local maxima for tracking objects. Therefore, in large target movement between two consecutive frames, the local and global modes are not the same as previous frames so that Mean Shift tracker may fail in tracking the desired object via localizing the global mode. To overcome this problem, a multibandwidth procedure is proposed to help conventional MS tracker reach the global mode of the density function using any staring points. This gradually smoothening procedure is called Multi Bandwidth Mean Shift (MBMS) which in fact smoothens the Kernel Function through a multiple kernel-based sampling procedure automatically. Since it is important for us to have less computational complexity for real-time applications, we try to decrease the number of iterations to reach the global mode. Based on our results, this proposed version of MS enables us to track an object with the same initial point much faster than conventional MS tracker.

Part-based recognition of vehicle make and model

Fine-grained recognition is a challenge that the computer vision community faces nowadays. The main category of the object is known in this problem and the goal is to determine the subcategory or fine-grained category. Vehicle make and model recognition (VMMR) is a hard fine-grained classification problem, due to the large number of classes, substantial inner-class and small inter-class distance. In this study, a novel approach has been proposed for VMMR based on latent SVM formulation. This approach automatically finds a set of discriminative parts in each class of vehicles by employing a novel greedy parts localisation algorithm, while learning a model per class using both features extracted from these parts and the spatial relationship between them. An effective and practical multi-class data mining method is proposed to filter out hard negative samples in the training procedure. Employing these trained individual models together, the authors’ system can classify vehicles make and model with a high accuracy. For evaluation purposes, a new dataset including more than 5000 vehicles of 28 different makes and models has been collected and fully annotated. The experimental results on this dataset and the CompCars dataset indicate the outstanding performance of the authors’ approach.

Hand Tracking Using Kernel Density Approximation

Abstract-In this paper, a new method is proposed for hand tracking based on a density approximation and optimization method. Considering tracking as a classification problem, we train an approximator to recognize hands from its background. This procedure is done by extracting feature vector of every pixel in the first frame and then building an approximator to construct a virtual optimized surface of pixels for similarity of the frames which belong to the hand of those frames related to the movie. Received a new video frame, approximator is employed to test the pixels and build a surface. In this method, the features we use is color RGB corresponding to the feature space. Conducting simulations, it is demonstrated that hand tracking based on this method result in acceptable and efficient performance. The experimental results agree with the theoretical results.

A cascading scheme for speeding up multiple classifier systems

Abstract The accuracy of multi-class classification problems is improving at a good pace. However, improving the accuracy often leads to slowing down the processing speed. Since employing a large number of classifiers or a combination of them is a time-consuming process, the sluggish behavior is more evident in multiple classifier systems. In this paper, a practical cascading scheme is proposed for boosting the speed of a multiple binary classifier system with no noticeable reduction in recognition rate. The proposed cascading scheme sets a sequence of binary classifiers and applies one classifier at a time to the input. Some effective criteria for a practical ordering of classifiers are introduced, and a fusion of them is verified to be the best. A vehicle make and model recognition (VMMR) system with multiple individual classifiers is presented briefly as a use case for a multi-class classification problem. The experiments done on this VMMR system using two completely different datasets confirm the effectiveness of our scheme. One of the configurations of the proposed scheme results in up to 30% speedup in comparison with the baseline VMMR system with analogous recognition rate. Another configuration of the proposed cascading scheme achieves up to 80% speedup with just a minor drop in accuracy.

A neuro-fuzzy fan speed controller for dynamic management of processor fan power consumption

The progress in silicon process technology have prepared the processors with more amount of cores. The more cores lead to increase the amount of required power. Therefore, the heat will be increased for the shortage of die size. The high temperature can cause degradation in performance, reliability, transistor aging, transition speed, and an increase in leakage current. One of the primitive thermal management technique is to use cooling equipment which can decrease temperature with no performance reduction. Although the high speed of fan reduces the temperature, it also brings the more power consumption. The increase in fan speed causes an increase in power consumption, large noise levels in the system, and a decrease of fan lifetime that may impact reliability. The Neuro-Fuzzy (NF) fan speed controller (NFSC) that we offered decreases fan power consumption while preventing the temperature violation from an expected temperature. NFSC estimates the minimum required fan speed that holds the temperature close to the desired temperature with the aim of saving power. The primarily practical results demonstrate that our suggested model in compared with the traditional fan controller is significantly able to reduce the average of fan power consumption approximately 30% with increasing of average temperature by 9% (4.7°C) compared to the traditional fan controller.

A neuro-fuzzy fan speed controller for dynamic thermal management of multi-core processors

Cooling equipments is a thermal management technique that reduces the thermal resistance of the heat sink without any performance degradation. However, higher fan speed produces a lower thermal resistance, but at the expense of higher power consumption. Our proposed Neuro-Fuzzy fan controller (NFSC), minimizes fan power consumption while avoiding the temperature increase above a certain threshold. The experimental results indicate that our proposed model can significantly decrease the average fan power with negligible temperature overhead compared to the traditional fan controller.

The methodology design of low-power hybrid-cascade compensation operational amplifiers based on settling behavior

Operational amplifiers used in switch-capacitance applications must have high speed, high accuracy and low power consumption. In this paper a design method for a two-stage hybrid-cascade compensation operational amplifier based on settling behavior in closed-loop applications is proposed. This methodology, which optimizes the relationship between settling-time and bandwidth of an amplifier, has been used in designing operational amplifiers of a broad-band Sigma-Delta Modulator that its settling accuracy is important. Utilizing this simple but accurate method has the better performance in power consumption and settling behavior, compared to the conventional methods.