Ali Vahdati

A 97–106-GHz differential I-Q phase shifter in 28-nm CMOS

This paper presents the design and corresponding measurement results of a W-Band differential I-Q phase shifter in 28-nm CMOS technology. Design of CMOS active switches and passive components like a 90° hybrid realized for differential I-Q operation are shown. The phase of the RF signal can be varied from 0° to 270° in steps of 90°. The measured input and output matching are better than -10 dB, and the maximum output imbalance is 0.8 dB with a maximum phase error of 19.6° at 100 GHz. Using a 1-V supply voltage, the total power consumption is 39 mW. The die area is 0.458 mm2.

Design of an 85–95-GHz differential amplifier in 28-nm CMOS FDSOI

This paper presents the design and measurement results of a W-band two-stage differential amplifier using transformers in 28-nm CMOS FDSOI. At 90 GHz, the amplifier achieves 13.8 dB gain, and the input and output return loss are -8.0 dB and -11 dB, repectively. The amplifier obtains +5 dBm saturated output power and 1-dB output compression point of 0 dBm at the centre frequency. From 85 to 95 GHz, the gain is better than 12.3 dB and the average noise figure (NF) is 8 dB. The design consumes 37.5 mW power from a 1-V supply and the active area of the design is 0.017 mm2.

A 124–184 GHz amplifier using slow-wave transmission lines in 28-nm FDSOI CMOS process

This paper presents a 124 to 184 GHz single-ended amplifier designed in 28-nm FDSOI CMOS technology. The amplifier consists of four common-source gain stages and broadband matching networks for input, output and inter-stage matching employing slow-wave shielded co-planar waveguides. Having a total power consumption of 31 mW, the amplifier achieves a peak gain of 10.1 dB at 167 GHz and a 3-dB bandwidth of 61 GHz.

Design of a W-Band 2-bit differential CMOS phase shifter

This paper presents the design of a W-Band I-Q phase shifter and the corresponding simulation results in 28-nm CMOS technology. The design of passive components like a 90° hybrid and transformers needed to realize differential I-Q operation is shown. The phase of the RF signal can be varied from 0° to 270° in steps of 90°. The simulated input and output matching are better than -10 dB, and the maximum phase error is roughly 10° with a maximum output imbalance of 0.5 dB at 90 GHz using a 1-V supply voltage. The total power consumption is 41 mW and the die area is 0.46 mm2.

A 53–117 GHz LNA in 28-nm FDSOI CMOS

This letter presents the design of a wideband millimeter-wave (mm-wave) low-noise amplifier (LNA) in a 28-nm FDSOI CMOS technology. Having a total power consumption of 38.2 mW, the LNA provides gain over 12 dB from 53 to 117 GHz, and has a measured NF of 6 dB from 75 to 105 GHz. To the author’s best knowledge, the presented LNA achieves the lowest NF with widest bandwidth among previously presented wideband CMOS LNAs operating in the W-band.

Design of a D-Band CMOS Amplifier Utilizing Coupled Slow-Wave Coplanar Waveguides

This paper validates a design and modeling methodology of coupled slow-wave waveguides (CS-CPW) by presenting a D-band CMOS low-noise amplifier (LNA) that utilizes the CS-CPW for impedance matching. The robustness and feasibility of using the CS-CPW as a matching element in wideband millimeter-wave (mm-wave) silicon circuit designs are studied. Furthermore, the key design details of a mm-wave LNA are discussed. The designed monolithic microwave integrated circuit amplifier has a gain greater than 10 dB from 135 to 170 GHz with a peak gain of 15.7 dB at 160 GHz. The amplifier has a measured noise figure of 8.5 dB from 135 to 170 GHz, and an output-referred 1-dB compression point of −16.5 dBm at 160 GHz. The total power consumption of the amplifier is 32 mW.

90 GHz CMOS Phased-Array Transmitter Integrated on LTCC

This paper presents the design of a 90 GHz phased-array transmitter front end on low-temperature co-fired ceramic (LTCC) technology. The monolithic microwave integrated circuit components have been fabricated by the CMOS technology and flip chipped on the LTCC to realize the transmitter front end. The dc and differential hybrid IF signals are provided to the flip-chipped components through the bias and IF lines designed on the LTCC. An

Wideband millimeter-wave active and passive mixers in 28 nm bulk CMOS technology

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A 100-GHz phase shifter in 28-nm CMOS FDSOI

patch antenna array has been designed for the transmitter and fabricated on the LTCC. The dc and IF signal pads on the LTCC were soldered to the designed printed circuit board pads for measurements. The measurement results show that by using a receiver horn antenna, the maximum received power at 92 GHz is −37.3 dBm at a communication distance of 1 m. The transmitter is capable of providing ±25° beam steering with respect to boresight and 20° half-power beamwidth at 90 GHz. The total power consumption of the transmitter front end is 656 mW.