Dristy Parveg

Experimental Verification of a Plane-Wave Field Synthesis Technique for MIMO OTA Antenna Testing

This paper evaluates the feasibility of a plane-wave field synthesis (PWS) technique for multiple-input multiple-output (MIMO) over-the-air (OTA) test facility, where a reference channel model is implemented. The test facility is based on a fading emulator and an anechoic chamber, equipped with multiple field emulating probes. The test facility emulates a radio channel condition using the PWS technique, based on the spherical wave theory. A simulation tool implementing the MIMO OTA field synthesis based on the PWS technique, named WIN-OTA, is established, where the WINNER II is chosen as the reference channel model. The simulation results show that the PWS technique reproduces the reference channels accurately in terms of envelope distribution, spatial and temporal correlation, and channel capacity. The WIN-OTA implementation was verified by comparing the emulated fields and the throughput from the simulations with the measurements for a practical MIMO OTA test facility. The results support the feasibility and accuracy of the field synthesis technique and the WIN-OTA implementation in MIMO OTA antenna testing.

CMOS I/Q Subharmonic Mixer for Millimeter-Wave Atmospheric Remote Sensing

A compact second harmonic 180 GHz I/Q balanced resistive mixer is realized in a 32-nm SOI CMOS technology for atmospheric remote sensing applications. The MMIC further includes two on-chip IF amplifiers at the mixers I and Q channels. A conversion gain of +8 dB is achieved with 74 mW of dc power consumption using a 1.2 V supply. The measured IF frequency range is from 1 to 10 GHz. The mixer achieves a 20 dB imagerejection (IR) ratio with an LO input power of +4 dBm. The chip size is 0.75 mm2 including probing pads.

A 97–106-GHz differential I-Q phase shifter in 28-nm CMOS

This paper presents the design and corresponding measurement results of a W-Band differential I-Q phase shifter in 28-nm CMOS technology. Design of CMOS active switches and passive components like a 90° hybrid realized for differential I-Q operation are shown. The phase of the RF signal can be varied from 0° to 270° in steps of 90°. The measured input and output matching are better than -10 dB, and the maximum output imbalance is 0.8 dB with a maximum phase error of 19.6° at 100 GHz. Using a 1-V supply voltage, the total power consumption is 39 mW. The die area is 0.458 mm2.

Design of an 85–95-GHz differential amplifier in 28-nm CMOS FDSOI

This paper presents the design and measurement results of a W-band two-stage differential amplifier using transformers in 28-nm CMOS FDSOI. At 90 GHz, the amplifier achieves 13.8 dB gain, and the input and output return loss are -8.0 dB and -11 dB, repectively. The amplifier obtains +5 dBm saturated output power and 1-dB output compression point of 0 dBm at the centre frequency. From 85 to 95 GHz, the gain is better than 12.3 dB and the average noise figure (NF) is 8 dB. The design consumes 37.5 mW power from a 1-V supply and the active area of the design is 0.017 mm2.

A 124–184 GHz amplifier using slow-wave transmission lines in 28-nm FDSOI CMOS process

This paper presents a 124 to 184 GHz single-ended amplifier designed in 28-nm FDSOI CMOS technology. The amplifier consists of four common-source gain stages and broadband matching networks for input, output and inter-stage matching employing slow-wave shielded co-planar waveguides. Having a total power consumption of 31 mW, the amplifier achieves a peak gain of 10.1 dB at 167 GHz and a 3-dB bandwidth of 61 GHz.

A 53–117 GHz LNA in 28-nm FDSOI CMOS

This letter presents the design of a wideband millimeter-wave (mm-wave) low-noise amplifier (LNA) in a 28-nm FDSOI CMOS technology. Having a total power consumption of 38.2 mW, the LNA provides gain over 12 dB from 53 to 117 GHz, and has a measured NF of 6 dB from 75 to 105 GHz. To the author’s best knowledge, the presented LNA achieves the lowest NF with widest bandwidth among previously presented wideband CMOS LNAs operating in the W-band.

Design of mixers for a 130-GHz transceiver in 28-nm CMOS

A compact and 3-dB bandwidth of 118-145-GHz Gilbert-cell mixer for up-conversion and a 1-dB bandwidth of 106-143-GHz image-rejection (IR) resistive mixer for down-conversion are designed for a 130-GHz transceiver in 28-nm CMOS technology. A wide 10-GHz intermediate frequency (IF) tuning range is obtained for both mixers. The simulated results show a +1.6-dB conversion gain for the Gilbert-cell mixer with a layout size of 720×633 μm2 and 6.1 mW of DC power consumption. An 11-dB conversion loss and 30-dB IR ratio are simulated for the resistive mixer with a layout size of 845×794 μm2. The simulated 1-dB output compression point is -8 dBm for the Gilbert-cell mixer and 1-dB input compression point is +9 dBm for the resistive mixer.

Design of a D-Band CMOS Amplifier Utilizing Coupled Slow-Wave Coplanar Waveguides

This paper validates a design and modeling methodology of coupled slow-wave waveguides (CS-CPW) by presenting a D-band CMOS low-noise amplifier (LNA) that utilizes the CS-CPW for impedance matching. The robustness and feasibility of using the CS-CPW as a matching element in wideband millimeter-wave (mm-wave) silicon circuit designs are studied. Furthermore, the key design details of a mm-wave LNA are discussed. The designed monolithic microwave integrated circuit amplifier has a gain greater than 10 dB from 135 to 170 GHz with a peak gain of 15.7 dB at 160 GHz. The amplifier has a measured noise figure of 8.5 dB from 135 to 170 GHz, and an output-referred 1-dB compression point of −16.5 dBm at 160 GHz. The total power consumption of the amplifier is 32 mW.

A 180-GHz CMOS down-converter MMIC for atmospheric remote sensing applications

In this paper, we study the feasibility of using CMOS circuit blocks for designing future light weight, small in size atmospheric remote sensing receivers. A compact CMOS down-converter is designed which operates from 160 to 188 GHz and includes a sub-harmonically pumped I/Q resistive mixer, two IF amplifiers and a voltage controlled oscillator (VCO) with LO buffer. A measured down-conversion gain of +2.6 dB is achieved with a total dc power consumption of 152 mW using the nominal supply of +1.2 V. The measurement results show a 3 dB IF bandwidth from 1 to 5 GHz and the VCO tuning range is from 85 to 89 GHz. The designed CMOS MMIC down-converter including the probing pads occupies a silicon area of 0.575 mm2.

Design of high-performance E-band SPDT switch and LNA in 0.13 μm SiGe BiCMOS technology

This paper presents the design of high-performance E-band single-pole double-through (SPDT) switch and low noise amplifier (LNA) as a part of transceiver front-end in an 0.13 μm SiGe BiCMOS technology. The quarter-wave shunt SPDT switch is designed using reverse-saturated SiGe HBTs. The resulting switch exhibits an insertion loss of 2.1 dB, isolation of 26 dB, reflection coefficient better than 18 dB at 75 GHz and provides a bandwidth of more than 35 GHz. The designed switch is integrated with a single-in differential-output (SIDO) low noise amplifier (LNA) and utilized as input matching element of the LNA. The LNA utilizes a common-emitter amplifier at the first stage and a casocode amplifier at the second stage to exploit the advantages of both common-emitter and cascode topologies. The resulting LNA with integrated switch achieves a gain and noise figure(NF) of 26 dB and 6.9 dB, respectively at 75 GHz with a 3 dB bandwidth of 12 GHz. Output referred 1-dB compression point of +5.5 dBm is achieved at 75 GHz. The designed integrated block consumes 45.5 mW of DC power and occupies an area of 720 μm × 580 μm excluding RF pads.