Ali Zeki

The dual-X current conveyor (DXCCII): a new active device for tunable continuous-time filters

In this work, a new active device, namely the dual-X current conveyor is proposed for linear tunable continuous-time filtering. The proposed device avails tunability with the aid of triode MOSFETs, while keeping large-signal linearity high. Besides linearity enhancement, the dual-X structure of the active device brings interesting features, which help reduce the required number of active devices and MOSFET resistors in a MOSFET-C continuous-time filter. Also, unlike most MOSFET-C filter structures, there does not exist a matching requirement for the utilized MOSFETs. A CMOS implementation and two application examples (a current mode Tow-Thomas biquad and a current-mode sinusoidal oscillator) are supplied and simulated to reveal the important advantages.

Integrated cross-coupled chaos oscillator applied to random number generation

A new cross-coupled LC chaos oscillator suitable for IC realisation is presented. The proposed circuit was fabricated using a 0.35 mum CMOS process and test results showing its feasibility are given. As a possible application, a method for using the proposed oscillator as the core of a random number generator is described. Experimental binary data obtained according to the proposed method pass the four tests of FIPS-140-2, the full NIST-800-22 and DIEHARD random number test suites.

Current-Steering Digital-to-Analog Converters: Functional Specifications, Design Basics, and Behavioral Modeling

Functional specifications and design basics for current-steering digital-to-analog converters (DACs) are covered. An outline of digital-to-analog conversion principles, together with fundamental current-steering DAC architectures, are briefly explained. A generalized design flow for DACs and design basics for current-steering architectures, together with a universal SIMULINK®-based behavioral model useful for the block-level simulation of a current-steering DAC, are described.

Generalized gyrator implementation techniques using unity-gain cells

All possible gyrator circuits using the minimum number of voltage and current unity-gain cells are extracted, as a result of generalizing the unity gains, such that a unity gain can be + 1 or −1. Since second-generation current conveyors (CCIIs), possessing both voltage and current unity-gain cells, are very suitable for such gyrators, it is shown that inclusion of the recently proposed ‘inverting secondgeneration current conveyor’ (ICCII) in the design enables implementation of all types of extracted gyrators. The number of possible gyrator configurations is eight, one of them being the well-known Sedra–Smith gyrator and another its x -input counterpart; both utilize only CCIIs. The remaining possible six gyrators are new and utilize ICCIIs as well. Like the Sedra–Smith gyrator, all the circuits employ a minimum number of passive elements and similar types of active components, namely CCIIs and/or ICCIIs. The effects of current conveyor non-idealities and parasitics on important gyrator applications are also investigated. A highperformance dual-output CMOS ICCII is designed and used in SPICE simulations of two important gyrator applications in order to verify the theoretical results. Also, as a design example, an elliptic filter is realized and simulated.

Realization of high-Q bandpass filters using CCCIIs

A new configuration for the realization of very high-Q filters with electronically controllable filter parameters is presented. For this purpose, first, a modification for the translinear CMOS CCCII and then, a new high-performance first-order allpass filter section are proposed. The main parameters of the resulting high-Q bandpass filter, ie. the center frequency and pole-Q can be independently adjusted via DC bias currents. It is also shown that the filter sensitivities with respect to capacitors mid intrinsic resistances are low. SPICE simulation results verify the theoretical analyses.

High-linearity low-voltage self-cascode class AB CMOS current output stage

A novel cascode current mirror structure is proposed, which is suitable for use in low-voltage current output stages. The current mirror makes use of the self-cascode structure and partial positive-feedback to reduce the input and output voltage restrictions. All devices are aimed to be kept in saturation to achieve a high output impedance. Besides known ones, further possibilities are investigated to keep all devices in saturation. It is also shown that, to enhance the output impedance, the regulated cascode scheme can be adopted with a minimum number of additional devices, without degrading the mirroring accuracy. A class AB CMOS current output stage employing the proposed current mirrors is simulated with PSpice so as to verify the mentioned performance characteristics.

New MOSFET model suitable for analogue IC analysis

A static MOSFET model suitable for analogue integrated circuit analysis has been evolved. It was considered that an active device model for analogue IC analysis should represent the device nonlinear conductance-voltage dependence adequately as well as current-voltage relation. The most important characteristics, I D-V DS and gds-VDS have been properly modelled. Precedence has been given to the modelling of channel-length modulation, which is the most dominant effect causing non-linearities of the I D-V DS and gds-V DS characteristics in the saturation region. With the aid of the developed model, I D-V DS and gds-VDS curves for an NMOS and a PMOS transistor have been estimated and are seen to fit adequately with the curves obtained from measurements. Distortion analysis using the new model has been carried out for a CMOS active-loaded amplifier to check the adequacy of the new model for analogue IC analysis. The results obtained are similar to the experimental results.

AN ADC BASED RANDOM BIT GENERATOR BASED ON A DOUBLE SCROLL CHAOTIC CIRCUIT

An A/D converter based random bit generator which exploits continuous-time chaos is presented. The chaotic circuit, which is used as the core of the random bit generator generates double-scroll attractor the frequency spectrum of which spans up to 80 MHz. The chaotic circuit was fabricated using a 0.35 μm CMOS process and the chip area, excluding pads, is 0.06 mm2. Power consumption of the integrated chip is 8 mW. Binary data obtained from the presented random bit generator pass the full NIST-800-22 test suite.

A high-speed swing reduced driver suitable for current-steering digital-to-analog converters

A driver circuit with a reduced swing to serve as a gate driver for steering switches of current-steering digital-to-analog converters (DACs) is designed. The swing reduced driver (SRD) reduces the digital signal feedthrough to the output node of the converter by decreasing the voltage swing at the gates of the switching transistors. The proposed SRD is suitable for operation at high speed. The circuit can be designed to maintain the voltage swing in the desired range without compromising seriously the area of the digital circuit. The designed circuit is validated through simulations of an application designed using the AMS 0.35µm CMOS process parameters.

Behavioral model of segmented current-steering DAC by using SIMULINK ®

A behavioral model is developed for segmented current-steering DAC. System is modeled by constructing a set of subsystems in SIMULINK® environment. To validate the model a 12-bit segmented current-steering DAC is modeled and performance characteristics are investigated for the worst case operation of the system. Simulation results confirm the accuracy of the model.