Indrit Myderrizi

FPGA Implementation of BASK-BFSK-BPSK Digital Modulators [Testing Ourselves]

Field-programmable gate-array (FPGA) implementations of binary amplitude-shift keying (BASK), binary frequency-shift keying (BFSK), and binary phase-shift keying (BPSK) digital modulators are presented. The proposed designs are aimed at educational purposes in a digital communication course. They employ the minimum number of blocks necessary for achieving BASK, BFSK, and BPSK modulation, and for full integration with the other functional parts of the Altera Development and Education (DE2) FPGA board. The input carrier signal and the bit stream (modulating signal) are user controllable. These digital modulators were developed and compiled to a Verilog Hardware Description Language (HDL) netlist, and were later implemented into an Altera DE2 FPGA board. The functionality of these digital modulators was demonstrated through simulations using the Quartus II simulation software, and experimental measurements of the real-time modulated signal via an oscilloscope.

An Electronically Fine-Tunable Multi-Input–Single-Output Universal Filter

A new electronically fine-tunable multi-input-single-output (MISO) universal filter is proposed. The filter circuit compared with active-device-based counterparts is very simple and fully integrable. Moreover, a few number of active transistors provide a reduction in power consumption, and the filter enjoys advantages such as no component matching and small size area. Postlayout simulation results using parameters of AMS CMOS 0.35-μm process technology show good agreement with theoretical expectations.

Current-Steering Digital-to-Analog Converters: Functional Specifications, Design Basics, and Behavioral Modeling

Functional specifications and design basics for current-steering digital-to-analog converters (DACs) are covered. An outline of digital-to-analog conversion principles, together with fundamental current-steering DAC architectures, are briefly explained. A generalized design flow for DACs and design basics for current-steering architectures, together with a universal SIMULINK®-based behavioral model useful for the block-level simulation of a current-steering DAC, are described.

A high-speed swing reduced driver suitable for current-steering digital-to-analog converters

A driver circuit with a reduced swing to serve as a gate driver for steering switches of current-steering digital-to-analog converters (DACs) is designed. The swing reduced driver (SRD) reduces the digital signal feedthrough to the output node of the converter by decreasing the voltage swing at the gates of the switching transistors. The proposed SRD is suitable for operation at high speed. The circuit can be designed to maintain the voltage swing in the desired range without compromising seriously the area of the digital circuit. The designed circuit is validated through simulations of an application designed using the AMS 0.35µm CMOS process parameters.

Behavioral model of segmented current-steering DAC by using SIMULINK ®

A behavioral model is developed for segmented current-steering DAC. System is modeled by constructing a set of subsystems in SIMULINK® environment. To validate the model a 12-bit segmented current-steering DAC is modeled and performance characteristics are investigated for the worst case operation of the system. Simulation results confirm the accuracy of the model.

CCII+ based fully CMOS four-quadrant multiplier

In this paper, a new fully CMOS four-quadrant multiplier based on plus-type second-generation current conveyors (CCII+s) is presented. The proposed circuit employs only two CCII+s and two NMOS transistors as active devices, without the need for any external passive elements. Functionality of the new circuit is demonstrated through SPICE simulations performed using 0.25μm CMOS process technology parameters. In addition, simulation results of an amplitude modulator realized with the proposed multiplier are included.

BiCMOS current-mode integrators suitable for low-voltage continuous-time filters

BiCMOS current-mode integrators suitable for low-voltage continuous-time filters are proposed, offering low-voltage operation, high speed and wide-range tuning. When compared with other BiCMOS structures, they offer simplicity in design without requiring extra cost. Various continuous-time filters are implemented from the proposed integrators and tuning methods are developed for these filters. The simulation results are in good agreement with the expectations.

A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology

With the increase in demand for high-speed and low-power integrated circuits as technology scales down, low-swing signaling circuit techniques are critical for providing high-speed low-power communications. However, existing low-swing circuits comprise complex designs, power issues (static and dynamic), output voltage swing restrictions or nonadjustable voltage swing levels, leading to lower operation speeds and even larger area footprints. In this paper, a tunable swing-reduced driver (SRD) circuit featuring the mentioned design challenges is presented. The SRD enables low-swing signals with fully controllable output voltage swing that is useful to reduce the power dissipation and delay in the signaling paths. Implemented in UMC 0.13-μm multi-threshold CMOS process, the SRD achieves 26 ps propagation delay at 200mV output swing for a pulse signal input at 1GHz. Post-layout simulations of the proposed SRD and a DAC application circuit, incorporating the SRD, operating at 1GHz, validate the design.