Alice C. Kilgo

Intermetallic compound layer formation between copper and hot-dipped 100In, 50In-50Sn, 100Sn, and 63Sn-37Pb coatings

The growth kinetics of intermetallic compound layers formed between four hot-dipped solder coatings and copper by solid state, thermal aging were examined. The solders were l00Sn, 50In-50Sn, 100In, and 63Sn-37Pb (wt.%); the substrate material was oxygen-free, high conductivity Cu. The total intermetallic layer of the 100Sn/Cu system exhibited a combination of parabolic growth at lower aging temperatures and t0.42 growth at the higher temperatures. The combined apparent activation energy was 66 kJ/mol. These results are compared to the total layer growth observed with the 63Sn-37Pb/Cu system which showed parabolic kinetics at similar temperatures and an apparent activation energy of 45 kJ/mol. Both 100Sn and 63Sn-37Pb diffusion couples showed a composite intermetallic layer comprised of Cu3Sn and Cu6Sn5. The intermetallic compound layer formed between In and Cu changed from a CuIn2 stoichiometry at short annealing times to a Cu57In43 composition at longer periods. The growth kinetics were parabolic with an apparent activation energy of 20 kJ/mol. The intermetallic layer growth of the 50In-50Sn/Cu system exhibited extreme variations in the layer thicknesses which prohibited a quantitative assessment of the growth kinetics. The layer was comprised of two compounds: Cu26Sn13In8 which was the dominant phase and a thin layer of Cu17Sn9In24 adjacent to the solder.

Intermetallic compound layer growth by solid state reactions between 58Bi-42Sn solder and copper

Solid state intermetallic compound layer growth was examined following ther-mal aging of the 58Bi-42Sn/Cu couple for a temperature range of 55 to 120°C and time periods of from 1 to 400 days. The intermetallic compound layer was comprised of sublayers that included the traditional Cu6Sn5 stoichiometry as well as one or more complex Cu-Sn-Bi chemistries. The number of sublayers increased with aging temperature and time. Time-dependent layer thickness computations based upon the empirical expression, Atn + B, revealed a time exponent, n, that decreased with increasing temperature from a maximum of 0.551 at 70°C to 0.417 at 120°C. The apparent activation energy for growth (at 100 days) was 55± 7 kJ/mol. The Bi-Sn/Cu data, together with that from the other solder/copper systems, suggested that at a given homologous temperature, the quantity of Sn in the solder field determines the intermetallic compound layer thickness as a function of time.

Solid state intermetallic compound layer growth between copper and hot dipped indium coatings

Solid state growth of intermetallic compound layers that form between hot dipped indium coatings and copper was investigated in diffusion couples aged at temperatures of 70, 100 and 135 °C and time periods of up to 300 days. At an annealing temperature of 70 °C, the metastable composition, Cu36In64, was observed at the interface. Ageing at 100 °C caused a dual layer structure with the Cu36In64 layer joined by a copper-rich intermetallic compound, Cu11In9, that is noted in the equilibrium phase diagram. An annealing temperature of 135 °C caused the eventual development of a single copper-rich intermetallic layer, Cu57In43, at the interface. Total intermetallic layer thickness was documented as a function of ageing time and temperature, exhibiting at1/2 dependence with an apparent activation energy of 20 kJ mol−1.

Failure Analysis Techniques for Microsystems-Enabled Photovoltaics

Microsystems-enabled photovoltaics (MEPV) has great potential to meet the increasing demands for light-weight, photovoltaic solutions with high power density and efficiency. This paper describes effective failure analysis techniques to localize and characterize nonfunctional or underperforming MEPV cells. The defect localization methods such as electroluminescence under forward and reverse bias, as well as optical beam induced current using wavelengths above and below the device band gap, are presented. The current results also show that the MEPV has good resilience against degradation caused by reverse bias stresses.

Ultra-thin single crystal silicon modules capable of 450 W/kg and bending radii <1mm: Fabrication and characterization

We present ultra-thin single crystal mini-modules built with specific power of 450 W/kg capable of voltages of >1000 V/cm2. These modules are also ultra-flexible with tight bending radii down to 1 mm. The module is composed of hundreds of back contact microcells with thicknesses of approximately 20 μm and diameters between 500-720 μm. The cells are interconnected to a flexible circuit through solder contacts. We studied the characteristics of several mini-modules through optical inspection, evaluation of quantum efficiency, measurement of current-voltage curves, and temperature dependence. Major efficiency losses are caused by missing cells or non-interconnected cells. Secondarily, damage incurred during separation of 500 μm cells from the substrate caused material detachment. The detachment induced higher recombination and low performance. Modules made with the larger cells (720 μm) performed better due to having no missing cells, no material detachment and optimized AR coatings. The conversion efficiency of the best mini module was 13.75% with a total Voc = 7.9 V.

Reliability model development for photovoltaic connector lifetime prediction capabilities

This paper describes efforts to characterize different aspects of photovoltaic connector reliability. The resistance variation over a population of connections was examined by measuring 75 connectors from three different manufacturers. The comparison shows differences in average resistance of up to 9% between manufacturers. The standard deviation of resistance among the same manufacturer ranged from 6%-11%. In a separate experiment, the corrosive effects of grime on the connector pins during damp heat accelerated testing at 85°C/85% RH were studied. We observed a small resistance increase in the first 100 hours of damp heat and no further changes up to the current 450 hours of available data. With the exception of one connector, the effects of grime on connector performance during accelerated testing could not be measured during this time period.

Thermal Fatigue and Failure Analysis of Cu-Plated Through Hole Solder Joints

A thermal cycle fatigue study and post-mortem failure analyses were conducted on through hole solder joints. Two types of joints were evaluated: connector-to-board and internal circuit board through holes (vias). The through hole vias in the former assemblies contain a Cu-based alloy pin, Fig. 1a, while those in the latter are either empty or solder-filled, Fig. 2a. In both assembly types, the via walls (barrels) are made from electroplated Cu. During thermal cycling, cracks develop in the Cu via walls, Figs. 1b and 2b. The thermal cycle employed was typical for assessment of high-reliability military and aerospace microelectronics, with temperature limits of -55°C and +125 ̊C, 15 min hold times, and ramp rates of 10°C/min. The effects of thermal cycling and partial solder filling on the propensity for Cu via cracking were investigated experimentally. The Cu fatigue cracking is caused by differential thermal expansion between the circuit board materials and the copper. Cross-sectional metallography was used to analyze the solder joints in the as-received condition and after 100, 200, 300, 500, and 1000 thermal cycles. The observations of via cracking were quantitatively summarized – the crack counting procedure is given in Ref. [1]. The phenomenon of thermalmechanical fatigue of the Cu-plated barrels was also simulated by finite element analysis (FEA).

Backside preparation and failure analysis for packaged microelectromechanical systems (MEMS)

Failure analysis tools and techniques that identify root cause failure mechanisms are key components to improving MEMS technology. Failure analysis and characterization are relatively simple at the wafer and die level where chip access is straightforward. However, analysis and characterization of packaged parts or components encapsulated with covers, caps, etc may be more cumbersome and lead to problems assessing the root cause of failure. This paper will discuss two methods used to prepare the backside of the package/device to allow for failure analysis and inspection of different MEMS components without removing the cap, cover, or lid on the device and/or the package. One method for backside preparation was grinding and polishing the package for IR inspection. This method involved backfilling the package cavity with epoxy to hold the die in place. The other method involved opening a window through the backside of the package, exposing the die for IR inspection. Failure analysis results showed both methods of backside preparation were successful in revealing the failure mechanisms on two different MEMS technologies.

Accelerated aging and thermal-mechanical fatigue modelling of Cu-plated through holes with partial solder filling

The reliability of connector-to-board solder joints was investigated by accelerated aging experiments and finite element analysis (FEA), with a strain-based criterion for fatigue failure of Cu vias. The accelerated aging temperature cycle was ?55?C to +125?C. The pin/through hole solder joints were examined by metallography after test intervals up to 1000 thermal cycles. Partial solder filling of the joints was observed and attributed to Au contamination of the solder and thin solder gaps between the connector pins and Cu-plated vias. All fatigue cracks observed in the vias after thermal cycling were associated with partial solder filling of the joints. The effects of partial solder fill on failure location were confirmed by FEA and acceptable agreement was found between the predicted cycles to failure and the experimentally observed onset of via cracking. The model and experimental results were used to predict component lifetimes for milder thermal-cycle conditions typically found in service.

The impact of process parameters on gold elimination from soldered connector assemblies

Gold coatings are used on connector structures to maintain suitable solderability of the underlying Ni coating layer as well as to prevent surface corrosion during service. However, the likelihood of Au embrittlement in connector solder joints must be minimized by eliminating much of the Au plating from the surfaces using a hot solder dipping or “wicking” procedure prior to final assembly. It was observed that Au removal was most effective by using a double wicking process. Also, a higher soldering temperature improved the efficiency of the Au removal process. A longer soldering time during the wicking process did not appear to offer an appreciable improvement in Au removal. Because the wicking procedure was a manual process, it was found to be operator dependent.