Alisson V. Brito

Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC

An innovative technique to model and simulate partial and dynamic reconfiguration is presented in this paper Developed from modifications of the SystemC kernel, this technique can either be used at transaction level (TLM) or at register transfer level (RTL). At TLM it allows the modeling and simulation of higher-level hardware and embedded software, while at RTL the dynamic system behavior can be observed at signals level. The provided set of instructions promises a reduction in the design cycle. Compared with traditional strategies, information about dynamic and adaptive behavior will be available in an earlier stage,. An established application from the automotive domain is analyzed and illustrates the potential of the technique at TLM. The acquired results will assist in the choice of the best cost/benefit tradeoff regarding FPGA chip area.

Development and Evaluation of Distributed Simulation of Embedded Systems Using Ptolemy and HLA

Nowadays, embedded systems have a huge amount of computational power and consequently, high complexity. It is quite usual to find different applications being executed in embedded systems. Embedded system design demands for method and tools that allow the simulation and verification in an efficient and practical way. This paper proposes the development and evaluation of a solution for embedded modeling and simulation of heterogeneous Models of Computation (MoCs) in a distributed way by the integration of Ptolemy II and the High Level Architecture (HLA), a middleware for distributed discrete event simulation, in order to create an environment with high-performance execution of large-scale heterogeneous models. Experimental results demonstrate, that the use of a non distributed simulation for some situations can be infeasible, as well as the use of distributed simulation with few machines, like one, two or three computers. It was demonstrated that a speedup of factor 4 was acquired when a model with 4,000 thousands actors were distributed in 8 different machines.

A Distributed Simulation Platform using HLA for Complex Embedded Systems Design

Design complex embedded systems demands method and tools that allow the simulation and verification in an efficient and practical way. This paper proposes the development and evaluation of a distributed simulation platform of heterogeneous simulators based on High Level Architecture (HLA), a middleware for distributed discrete event simulation, in order to create an environment with high-performance execution of large-scale, heterogeneous and complex embedded systems. However, integrate hybrid systems is not trivial, because there is no guarantee that two systems that perfectly work separately will work well together. Experimental results of five different scenarios are presented, which integrate five different simulations tools: Ptolemy II, SystemC, Omnet++, Veins, Stage (a Robot Operating System compatible simulator) and physical robots. The experiments show success in application of Wireless Sensor Networks (WSN), power estimation of circuit design, robotic simulation and co-simulation of real robots.

The Study of a Dynamic Reconfiguration Manager for Systems-on-Chip

This paper presents the specification and designing of a Dynamic Configuration Manager for Dynamic Reconfigurable Systems-on-chip (DRSoC). The manager is compile time parameterizable to enable the modelling of different technology specific details from vendors like Xilinx, Altera or others. The manager is embedded into a simulation environment for proof of concept purposes. It is implemented in cycle accurate System C and enables system analysis considering its performance and power metrics. With that, it allows a quantification of a specific DRSoC implementation. A System C kernel extension exposes the basis of the Dynamic Reconfiguration mechanism. The manager is also designed in RTL and implemented on a Xilinx Virtex2Pro FPGA. This allows a characterization of performance and power figures and their back-annotation into the higher level System C environment, which provides a speed-up of 25 compared to RTL.

A General Purpose Partially Reconfigurable Processor Simulator (PReProS)

An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for dynamic reconfiguration. The presented approach can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level (RTL), if the dynamic system behavior is desired to be observed at signal level. The reconfigurable processor can be easily set to model the desired architecture in a behavioral but reasonable way. An example is presented where a XPP processor is implemented and simulated, executing typical applications. The resulting statistics assist either in the choice of the best cost/benefit configuration area that should be available on chip, or in the choice of the target architecture itself.

Functional verification of power gate design in SystemC RTL

With the growth of number of transistors, thermal density and market drive towards battery power, the necessity to develop low power integrated circuits is evident. There are several methodologies and techniques that help in the development of this type of SoC. There is consensus that the techniques when applied in the initial phases of the design flow, especially in design and architecture of the system have a higher impact factor in relation to those applied during the implementation or layout phase. Considering this fact, the possibility to accomplish functional verification of the system with low power design modeled in TLM and RTL is attractive. The purpose of this paper is to show a method for functional verification of power gate design in RTL. A case study is presented to demonstrate the application of power gate using new features for the OSCI SystemC simulator developed for this purpose and the accomplishment of the functional verification of the design using the VeriSC methodology.

Verification of Embedded System Designs through Hardware-Software Co-Simulation

This work proposes an environment for real- time testing of heterogeneous embedded systems through co- simulation. The verification occurs on real-time between the system software and hardware platform using the High Level Architecture (HLA) as a middleware between the hardware device and the simulated model. The novelty of this approach is not only providing support for simulations, but also allowing the synchronous integration with any physical hardware devices. In this paper we use the Ptolemy framework as a simulation platform. The integration of HLA with Ptolemy and the hardware models open a vast set of applications, like the test of many devices at the same time, running the same, or different applications or modules, the usage of Ptolemy for real-time control of embedded systems and the distributed execution of different embedded devices for performance improvement or collaborative execution. A case study is presented to prove the concept, showing the successful integration between the Ptolemy framework with an implementation using Atmel and ARM microcontrollers.

The Development of a Methodology with a Tool Support to the Distributed Simulation of Heterogeneous and Complexes Embedded Systems

Nowadays, embedded systems contains a big computational power and consequently a big complexity. It is very common to find different kinds of applications being executed in embedded systems. With this scenario, it is necessary some method and/or tool that allows the simulation of those systems in an efficient and practice way. The goal of this paper is to expose the integration between Ptolemy II and HLA in order to enable the elaboration of one methodology, with a tool support, to model and simulate large scale heterogeneous embedded systems.

A Methodology for Modelling and Simulation of Dynamic and Partially Reconfigurable Systems

In the present day, partial reconfiguration is a reality (Becker & Hartenstein, 2003). There are many industries investing as well in fine-grain (like FPGAs (Huebner et al., 2004)) as in coarse grain solutions (eg. XPP (Becker & Vorbach, 2003)). This capability enables the necessary configuration area to decrease and the development of lower cost and more energy efficient systems, where timing is the main concern. The main contribution of this work is to enable the engineers to discover earlier during the design-flow the best cost-benefit relationship between configuration time and saved chip area. Such relationship is generally obtained only after the prototyping phase during the hardware verification. Once the dynamic reconfiguration simulation is possible in a simple way, the concrete benefits of such simulations can be checked in a simple way. The innovative technique presented here allows the modeling and simulation of such systems by enabling new functions to module blocking and resuming in the simulator kernel. This enables the dynamic behavior to be foreseen before the synthesis on the target configuration (like FPGA). Furthermore, systems evaluation is possible even before their hardware description using a Hardware Description Language. Papers were published (Brito et al., 2006; Brito et al., 2007) presenting how the partial reconfiguration can be practically simulated. In this work a novel methodology for simulate partial and dynamic reconfigurable system is presented. This methodology can be applied to any hardware simulator which uses an event scheduler. The main idea is to register each block that is not configured on a chip at a given moment in simulated time. Modifying the simulator scheduler, it is programmed to not execute those blocked modules. We prove in this work that this approach covers every partial and dynamic reconfigurable system situation. SystemC is used as a case of study and several systems were simulated using our methodology. The section 2 presents what a simulator should implement to be considered able to simulate partial and dynamic systems. The methodology is presented on section 3 and section 4 presents how we applied it to SystemC. A particular strategy was adopted to log the chip area usage enabling the investigation of the benefits of dynamic reconfigurations in each application. This logging strategy is presented on section 5. Section 6 proves that the partial and dynamic reconfiguration can be really modeled and simulated using our methodology

A Framework for Analyzing Adaptive Autonomous Aerial Vehicles

Unmanned aerial vehicles (UAVs), a.k.a. drones, are becoming increasingly popular due to great advancements in their control mechanisms and price reduction. UAVs are being used in applications such as package delivery, plantation and railroad track monitoring, where UAVs carry out tasks in an automated fashion. Devising how UAVs achieve a task is challenging as the environment where UAVs are deployed is normally unpredictable, for example, due to winds. Formal methods can help engineers to specify flight strategies and to evaluate how well UAVs are going to perform to achieve a task. This paper proposes a formal framework where engineers can raise the confidence in their UAV specification by using symbolic, simulation and statistical and model checking methods. Our framework is constructed over three main components: the behavior of UAVs and the environment are specified in a formal executable language; the UAV’s physical model is specified by a simulator; and statistical model checking algorithms are used for the analysis of system behaviors. We demonstrate the effectiveness of our framework by means of several scenarios involving multiple drones.