Elmar U. K. Melcher

Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC

An innovative technique to model and simulate partial and dynamic reconfiguration is presented in this paper Developed from modifications of the SystemC kernel, this technique can either be used at transaction level (TLM) or at register transfer level (RTL). At TLM it allows the modeling and simulation of higher-level hardware and embedded software, while at RTL the dynamic system behavior can be observed at signals level. The provided set of instructions promises a reduction in the design cycle. Compared with traditional strategies, information about dynamic and adaptive behavior will be available in an earlier stage,. An established application from the automotive domain is analyzed and illustrates the potential of the technique at TLM. The acquired results will assist in the choice of the best cost/benefit tradeoff regarding FPGA chip area.

An automatic testbench generation tool for a SystemC functional verification methodology

The advent of new 90 nm/130 nm VLSI technology and SoC design methodologies, has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any design flow. New methods are required that allow for easier, quicker and more reusable verification. In this paper we propose an automatic verification methodology approach that enables fast, transaction-level, coverage-driven, self-checking and random-constraint functional verification. Our approach uses the systemC verification library (SCV), to synthesize a tool capable of automatically generating testbench templates. A case study from a real MP3 design is used to show the effectiveness of our approach.

FPGA architecture for static background subtraction in real time

Background subtraction is a method typically used to segment moving regions in image sequences taken from a static camera by comparing each new frame to a model of the scene background. In this paper, we present an FPGA architecture for background subtraction, taking advantage of the data and logical parallel opportunities offered by a field programmable gate array (FPGA) architecture. At a clock rate of 40 MHz, the architecture can process 30 frames per second, where the image resolution is 240 x 120. The capability of the system is demonstrated for several tests and video sequences.

An open-source tool for simulation of partially reconfigurable systems using SystemC

This paper presents a novel technique for simulation of dynamically and partially reconfigurable systems using SystemC. Its kernel was modified in order to enable the deactivation of any module at simulation time. An example of how to use this technique is presented. Simulations using our MPEG-4 decoder implementation are being developed

A Surface Plasmon Resonance Biochip That Operates Both in the Angular and Wavelength Interrogation Modes

This paper presents a surface plasmon resonance system based on a polymer prism chip. The device allows operation in both the angular and wavelength interrogation modes. The biochip design is discussed emphasizing the effect of the ambient temperature over the optical behavior. Birefringence effect, biochip polishing, and responsivity are also reported. The basic mathematical formulation for both operating modes is discussed, and morphological parameters are considered in the data analysis. Experimental sensorgrams obtained at both interrogation modes with the same polymer prism chip are presented and compared. The experimental sensorgrams obtained with assays providing reversible (phosphate buffered saline and hypochlorite solutions) and irreversible (neutravindin solution) bindings demonstrate the feasibility of the proposed design.

A methodology aimed at better integration of functional verification and RTL design

The advent of new 65 nm/90 nm VLSI technology and SoC design methodologies has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any digital design flow. Thus, new methods for easier, faster and more reusable verification are required. This paper proposes a verification methodology (VeriSC2) that guides the implementation of working testbenches during hierarchical decomposition and refinement of the design, even before the RTL implementation starts. This approach uses the SystemC Verification Library (SCV), in a tool capable of automatically generating testbench templates. A case study from a MPEG-4 decoder design is used to show the effectiveness of this approach.

FPGA-based SVPWM trigger generator for a 3/spl phi/ voltage source inverter

An FPGA-based space vector pulse width modulator (SVPWM) for use with a voltage source inverter is designed. The modulator is based on the comparison between the reference sinusoidal signals and a triangular carrier waveform. The carrier-based modulation is interpreted in terms of space vector theory. The design permits implementation of predefined modulation strategies and a user-designed strategy. The modulation configuration has been written in Verilog HDL code and typical modulator output pulses for different strategies have been presented.

A Distributed Simulation Platform using HLA for Complex Embedded Systems Design

Design complex embedded systems demands method and tools that allow the simulation and verification in an efficient and practical way. This paper proposes the development and evaluation of a distributed simulation platform of heterogeneous simulators based on High Level Architecture (HLA), a middleware for distributed discrete event simulation, in order to create an environment with high-performance execution of large-scale, heterogeneous and complex embedded systems. However, integrate hybrid systems is not trivial, because there is no guarantee that two systems that perfectly work separately will work well together. Experimental results of five different scenarios are presented, which integrate five different simulations tools: Ptolemy II, SystemC, Omnet++, Veins, Stage (a Robot Operating System compatible simulator) and physical robots. The experiments show success in application of Wireless Sensor Networks (WSN), power estimation of circuit design, robotic simulation and co-simulation of real robots.

A General Purpose Partially Reconfigurable Processor Simulator (PReProS)

An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for dynamic reconfiguration. The presented approach can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level (RTL), if the dynamic system behavior is desired to be observed at signal level. The reconfigurable processor can be easily set to model the desired architecture in a behavioral but reasonable way. An example is presented where a XPP processor is implemented and simulated, executing typical applications. The resulting statistics assist either in the choice of the best cost/benefit configuration area that should be available on chip, or in the choice of the target architecture itself.

An electro-thermal approach to dielectric breakdown in solids: application to crystalline polymer insulators

A dielectric breakdown model, linked to appearance of a singularity, has been developed and applied to a high purity alkane type (n-C36H74) insulator. The polymer material, which exhibits low defect / trap density, represents the single-crystalline iso-electronic analog to polyethylene. At high fields, and based on experimental findings, carrier transport is mediated by delocalized states in the conduction and valence band, respectively. Field induced impact ionization and carrier multiplication are triggered by hot carrier photoinjection above a critical field magnitude of 0.8 MV for holes and 1.26 MV for electrons, in accord with the band model. Associated critical sample thickness values have been estimated. The related electrical properties have been explored on the basis of the electrothermal heat balance equation. The non-linear differential equation has been solved numerically, with appropriate thermo-physical materials and carrier transport parameters, considering the dielectric breakdown phenomenon as a singularity. It leads to thermal run-away as a consequence of strong positive electro-thermal feedback, under conditions of initial transient behavior. Required thermo-physical parameters are attributed to and explain filamentary charge transport. The temporal evolution of temperature and current in the conducting filament during the breakdown event exhibits a time scale up to the microsecond range. The dynamic properties of the phenomenon are strongly affected by heat transfer from the conducting section into the surrounding nonconducting material, as well as the temporal characteristics of the initial trigger conditions.