Allan Ward

RF Performance and Reliability of SiC MESFETs on High Purity Semi-Insulating Substrates

In this paper we report on our efforts to reduce trap effects, increase efficiency, and improve the yield and reliability of SiC MESFETs. By minimizing substrate and surface-related trapping effects that have previously been observed in SiC MESFETs, drain efficiencies as high as 68% have been achieved at 3.5 GHz with associated CW power densities of 3.8 W/mm. MESFETs fabricated with this process have passed 1,000 hour High Temperature Reverse Bias test (HTRB) with negligible change in dc or RF parameters. A sampling of these devices have also been running for over 2,000 hours in an RF high temperature operating life test (HTOL) with negligible change in parameters. This MESFET process has been transferred to 3-inch high purity semiinsulating (HPSI) substrates. The quality of this process is demonstrated by the cross-wafer uniformity of the breakdown voltage and a standard deviation in gate threshold voltage of 0.6 V. Introduction SiC MESFETs have received increased attention in recent years due to their high power density and high operating voltage, which will enable wider bandwidth, higher performance, and lighter weight systems than those using conventional Si or GaAs technology. Significant progress has been achieved in the development and demonstration of high power MESFETs and wide band amplifiers based on this technology [1]. However, undesirable problems related to trapping in the substrate and/or the surface have also been reported [2-5]. These issues need to be fully resolved to improve device performance, reliability, and to make this technology commercially viable. In this paper we present our recent results for SiC MESFETs that exhibit minimal trap-related effects. Extensive data on the reliability of these devices is also presented. MESFET Performance The MESFETs in this work were fabricated on 2-inch diameter high-purity semi-insulating (HPSI) 4H-SiC substrates available from Cree. The MESFETs were fabricated with dry-etched isolation mesas, sintered Ni ohmic contacts, a gate length of 0.45 μm, and air-bridge source interconnects. These devices were fully passivated with 0.5 μm of silicon nitride for environmental protection and reliability. Devices fabricated with this process typically show maximum channel current, Imax, of 360 mA/mm, pinch-off voltage of –10 V, peak transconductance of 42 mS/mm, and gate-drain breakdown voltage in excess of 120 V. These DC characteristics translate to excellent RF performance in both Class A and deep Class AB conditions. Fig. 1 shows an on-wafer CW load pull measurement at 3.5 GHz of a 1-mm device biased at a very low bias current of 3% Imax and VDS=50 V. The power output is 3.8 W with an associated drain efficiency of 68%. The associated PAE under these conditions is typically in the range of 53% 58%. The high drain efficiency under near pinch-off condition clearly demonstrates that substrate and surface trapping effects previously observed in SiC MESFETs have been greatly reduced. Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 1205-1208 doi:10.4028/www.scientific.net/MSF.457-460.1205