Almudena Lindoso

Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection

Estimation of soft error sensitivity is crucial in order to devise optimal mitigation solutions that can satisfy reliability requirements with reduced impact on area, performance, and power consumption. In particular, the estimation of Single Event Transient (SET) effects for complex systems that include a microprocessor is challenging, due to the huge potential number of different faults and effects that must be considered, and the delay-dependent nature of SET effects. In this paper, we propose a multilevel FPGA emulation-based fault injection approach for evaluation of SET effects called AMUSE (Autonomous MUltilevel emulation system for Soft Error evaluation). This approach integrates Gate level and Register-Transfer level models of the circuit under test in a FPGA and is able to switch to the appropriate model as needed during emulation. Fault injection is performed at the Gate level, which provides delay accuracy, while fault propagation across clock cycles is performed at the Register-Transfer level for higher performance. Experimental results demonstrate that AMUSE can emulate soft error effects for complex circuits including microprocessors and memories, considering the real delays of an ASIC technology, and support massive fault injection campaigns, in the order of tens of millions of faults within acceptable time.

Analyzing the Impact of Single-Event-Induced Charge Sharing in Complex Circuits

This paper proposes a soft error characterization methodology to analyze multiple faults caused by single-event-induced charge sharing in standard-cell based ASIC designs. Fault injection campaigns have been executed using data provided by placement analysis as well as a pulse width modeling through electrical simulation. Experimental results demonstrate that the error rate can be largely overestimated if placement is not considered.

High performance FPGA-based image correlation

Image correlation is widely used for image and picture processing. Typical applications of image correlation are object location, image registration and sub-image similarity measurement. However, image correlation requires the comparison of a large number of sub-images implying a large computational effort that may prevent its use for real-time applications. On the other hand, correlation computation is very well suited for FPGA implementations. In this work we present efficient architectures for the implementation of Zero-Mean Normalized Cross-Correlation using FPGAs with application to image correlation. In particular, we compare the implementations of correlation in the spatial and spectral domains. Experimental results demonstrate that FPGAs improve performance by at least two orders of magnitude with respect to software implementations on a modern personal computer. This speed-up makes the performance of correlation computation suitable for real-time image processing. The proposed architectures have been applied to a correlation-based fingerprint-matching algorithm, demonstrating that real-time processing requirements can be well satisfied with an FPGA-based implementation.

Correlation-based fingerprint matching using FPGAs

Correlation based methods are gaining attention in the biometric field due to the extremely good results achieved for pattern matching recognition in authentication and verification processes. In particular, a high matching accuracy can be obtained with these methods in the fingerprint field. However, they cannot be used in many applications because of the large computational effort required. On the other hand, they are very well suited for FPGA implementations. In this work we present efficient architectures for implementation of zero mean normalized cross correlation using Virtex-4 FPGAs for application to correlation based fingerprint matching. In particular, we compare the implementations of correlation in the spatial and Fourier domains. Experimental results demonstrate that FPGAs allow improving performance by at least two orders of magnitude with respect to software implementations in a modern personal computer. Thanks to this speedup, correlation based algorithms for fingerprint matching achieve acceptable performance for real-time processing

Constrained placement methodology for reducing SER under single-event-induced charge sharing effects

This paper presents a methodology to reduce the impact of double faults in a circuit by constraining the placement of its standard cells. A fault-injection emulation platform is used to analyze the single-event-induced charge sharing effect in every pair of nodes. Based on the sensitivity of each pair, guidelines are set in a commercial standard cell placement by using constraints. Results show that by correctly choosing the nodes location, the error rate resulting from double faults can be reduced compared to single fault.

FPGA-Based Acceleration of Fingerprint Minutiae Matching

Fingerprint is the most widely used and studied biometric technique because of its universality, distinctiveness, and decreasing cost of the sensing devices. Among the fingerprint identification techniques, minutiae-based algorithms are the most mature. However, these methods are computationally expensive, particularly for comparison with large databases. This work is devoted to study the performance gains that can be achieved with the use of FPGAs. To this purpose, two minutia-based fingerprint matching algorithms have been selected and implemented in a FPGA in order to compare the requirements and performance of software and hardware implementations. Experimental results demonstrate the feasibility of implementing fingerprint matching algorithms in current FPGA devices achieving speed-ups of one or two orders of magnitude. Customization of the proposed implementations can lead to several architectures optimized in size, price, speed or accuracy.

Correlation-based fingerprint matching with orientation field alignment

Correlation-based techniques are a promising approach to fingerprint matching for the new generation of high resolution and touchless fingerprint sensors, since they can match ridge shapes, breaks, etc. However, a major drawback of these techniques is the high computational effort required. In this paper a coarse alignment step is proposed which reduces the amount of correlations that should be performed. Contrarily to other alignment approaches based on minutiae or core location, the alignment is based on the orientation field estimations. Also the orientation coherence is used to identify the best areas for correlation. The accuracy of the approach is demonstrated by experimental results with an FVC2000 fingerprint database. The approach is also very well suited for hardware acceleration due to the regularity of the used operations.

FPGA implementation for an iris biometric processor

Biometrics is nowadays one of the most promising techniques in authentication. Biometrics intends to identify a user by his/her physical and/or behavioural characteristic. Among all Biometric techniques, Iris recognition stands out, as its error rates are one of the lowest. The authors propose in this paper a hardware implementation based on FPGA for an iris biometric processor. By this solution a reduction of the processing time is obtained and security levels of the whole system are increased due to the reduction of software involved

Analysis of SET Effects in a PIC Microprocessor for Selective Hardening

In this work we propose a method to evaluate the criticality of the components of a circuit with respect to Single Event Transient (SET) effects. Emulation-based fault injection is used to determine the error rate for each individual gate. The method also identifies the optimal set of flip-flops to be hardened using time redundancy techniques. The results enable the selective application of SET mitigation techniques to satisfy soft error rate requirements with reduced overheads. A PIC18 microprocessor with three different workloads has been used as a case study, and results show that just hardening 25% of gates is enough to achieve more than 99% mitigation of SET effects.

Efficient Mitigation of Data and Control Flow Errors in Microprocessors

The use of microprocessor-based systems is gaining importance in application domains where safety is a must. For this reason, there is a growing concern about the mitigation of SEU and SET effects. This paper presents a new hybrid technique aimed to protect both the data and the control-flow of embedded applications running on microprocessors. On one hand, the approach is based on software redundancy techniques for correcting errors produced in the data. On the other hand, control-flow errors can be detected by reusing the on-chip debug interface, existing in most modern microprocessors. Experimental results show an important increase in the system reliability even superior to two orders of magnitude, in terms of mitigation of both SEUs and SETs. Furthermore, the overheads incurred by our technique can be perfectly assumable in low-cost systems.