Enrique San Millán

Analyzing the Impact of Single-Event-Induced Charge Sharing in Complex Circuits

This paper proposes a soft error characterization methodology to analyze multiple faults caused by single-event-induced charge sharing in standard-cell based ASIC designs. Fault injection campaigns have been executed using data provided by placement analysis as well as a pulse width modeling through electrical simulation. Experimental results demonstrate that the error rate can be largely overestimated if placement is not considered.

AKARI-X: A pseudorandom number generator for secure lightweight systems

In order to obtain more secure and reliable systems, the vast majority of RFID protocols include a Pseudorandom Number Generator (PRNG) in its design. However, the authors often do not specify the PRNG to use and standard solutions exceed the capabilities of low-cost RFID tags. In this paper, we propose two lightweight PRNGs (AKARI-1 and AKARI-2) that meet the requirements of these systems while improving their reliability and security. They may be supported on commercial tags of low price.

Efficient ASIC Implementation and Analysis of Two EPC-C1G2 RFID Authentication Protocols

The Internet of Things refers to the use of services provided by the networked objects (things) equipped with computational capabilities. A wide range of devices can be attached to objects to provide them with computing and networking functions, from RFID tags for identification purposes to a variety of wireless sensors. In the case of RFID technologies operating in the UHF band, the EPC Class-1 Generation-2 (EPC-C1G2) is one of the most established working frameworks. The security of this standard is quite low and many researchers have proposed over the last years alternative schemes aimed at correcting its multiple vulnerabilities. Unfortunately, the hardware implementation of such protocols has been long neglected, and it is unclear whether these proposals could fit a low-cost device where very few resources can be devoted to the security functions. In this paper, we address this question by reporting our experiences with the ASIC implementation of two representative EPC-C1G2 authentication protocols. We explore the design space and provide a detailed analysis of the area occupied by the synthesized circuits, their power consumption, and the throughput in terms of protocol runs per second. To the best of our knowledge, this is the first ASIC implementation of two lightweight protocols conforming the EPC-C1G2 specification. We believe that some of the discussion and insights here reported could be helpful to future implementations, both for RFID systems and resource-constrained sensors.

Constrained placement methodology for reducing SER under single-event-induced charge sharing effects

This paper presents a methodology to reduce the impact of double faults in a circuit by constraining the placement of its standard cells. A fault-injection emulation platform is used to analyze the single-event-induced charge sharing effect in every pair of nodes. Based on the sensitivity of each pair, guidelines are set in a commercial standard cell placement by using constraints. Results show that by correctly choosing the nodes location, the error rate resulting from double faults can be reduced compared to single fault.

Correlation-based fingerprint matching with orientation field alignment

Correlation-based techniques are a promising approach to fingerprint matching for the new generation of high resolution and touchless fingerprint sensors, since they can match ridge shapes, breaks, etc. However, a major drawback of these techniques is the high computational effort required. In this paper a coarse alignment step is proposed which reduces the amount of correlations that should be performed. Contrarily to other alignment approaches based on minutiae or core location, the alignment is based on the orientation field estimations. Also the orientation coherence is used to identify the best areas for correlation. The accuracy of the approach is demonstrated by experimental results with an FVC2000 fingerprint database. The approach is also very well suited for hardware acceleration due to the regularity of the used operations.

On the optimization power of redundancy addition and removal for sequential logic optimization

The paper attempts to determine the capabilities of existing redundancy addition and removal (SRAR) techniques for logic optimization of sequential circuits. To this purpose, we compare this method with the retiming and resynthesis (RaR) techniques. For the RaR case the set of possible transformations has been established by relating them to STG transformations by other authors. Following these works, we first formally demonstrate that logic transformations provided by RaR are covered by SRAR as well. Then we also show that SRAR is able to identify transformations that cannot be found by RaR. This way we prove the higher potential of the sequential redundancy addition and removal over the retiming and resynthesis techniques.

Fault Attacks on STRNGs: Impact of Glitches, Temperature, and Underpowering on Randomness

True random number generators (TRNGs) are the basic building blocks of cryptographic implementations. They are used to generate random numbers required for security protocols, to generate ephemeral keys, and are often used in hiding or masking countermeasures to thwart implementation attacks. The protection of TRNGs is an important issue to guarantee the security of cryptographic systems but less attention has been made in the past to evaluate the susceptibility of these building blocks against passive and active attacks. In this paper, we present active fault attacks on a recently proposed specific TRNG architecture presented by Cherkaoui et al. at CHES 2013. We successfully injected power and clock glitches in an FPGA implementation and elaborated the design in respect of thermo and underpowering attacks. Furthermore, we propose a method on how to reduce the susceptibility of these attacks to increase the resistance against fault attacks. To the best of our knowledge, this is the first work that evaluates practical clock-glitch-based fault attacks on self-timed ring-based TRNGs.

Increasing security with correlation-based fingerprint matching

The new generation of high resolution and touch-less fingerprint sensors can provide high resolution features, also known as level 3 features, in addition to macroscopic and microscopic features. Level 3 features matching will increase the system security to the governmental and Police levels. Unfortunately, traditional fingerprint matching techniques are not adapted to this new scenario and cannot exploit and match all the information the new fingerprints have confined inside them. In this paper a fingerprint matching algorithm that makes use of this new and relevant information is presented. The matching algorithm proposed is based in cross-correlation computation. Correlation uses the gray level information of the fingerprint image and can take into account all dimensional attributes of a fingerprint. In order to reduce the computational effort a coarse alignment step is performed beforehand. This alignment Is based in the cross-correlation of the orientation fields of the fingerprints. Region selection is performed to detect relevant information inside the fingerprint. For low resolution fingerprints the selection is based in the overlapping and the coherences of the orientation of both fingerprints. For high resolution fingerprints standard deviation of wavelet coefficients is also considered in the selection criterion. Experimental results demonstrate that this algorithm provides good results for both high and low resolution images.

Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness

Pseudorandom number generators (PRNGs) are used frequently in secure data processing algorithms. Randomness measuring is an essential test, performed on these generators, that help to range the security of the designed algorithm with respect to assure strong messing-up of the processed data. This paper describes a solution for accelerating statistical tests of Diehard Battery based on reconfigurable hardware, benefiting from task parallelization and high frequencies. With this proposal, users can obtain a fast, cheap and reliable measure of the randomness properties that can enable a complete exploration of the design space to produce better devices in shorter times.

An Estimator for the ASIC Footprint Area of Lightweight Cryptographic Algorithms

In resource-constrained devices such as RFID tags or implantable medical devices, algorithm designers need to make careful choices to ensure that their proposals are sufficiently efficient for the target platform. A common way of expressing such restrictions is in terms of an upper bound for the maximum available footprint area in gate equivalents (GE). For example, RFID tags conforming to standards EPC Class-1 Generation-2 and ISO/IEC 18000-6C can devote up to 4K GE to security functions. However, in most cases, algorithm designers are not hardware experts, nor they have any quantitative means to find out how much area their designs would occupy in a given technology. In this paper, we attempt to fill this gap by providing an estimate of the upper bound for the footprint area of any algorithm. Our approach takes into account the main components of such algorithms, namely, basic arithmetic/logic operations and additional hardware such as registers and multiplexers. We believe that our proposal can help designers in making informed decisions about what kind of algorithmic structures can be afforded for a target environment.