Alok Jain

Efficient Modeling of Memory Arrays in Symbolic Simulation

This paper enables symbolic simulation of systems with large embedded memories. Each memory array is replaced with a behavioral model, where the number of symbolic variables used to characterize the initial state of the memory is proportional to the number of memory accesses. The memory state is represented by a list containing entries of the form 〈c, a, d〉, where c is a Boolean expression denoting the set of conditions for which the entry is defined, a is an address expression denoting a memory location, and d is a data expression denoting the contents of this location. Address and data expressions are represented as vectors of Boolean expressions. The list interacts with the rest of the circuit by means of a software interface developed as part of the symbolic simulation engine. The interface monitors the control lines of the memory array and translates read and write conditions into accesses to the list. This memory model was also incorporated into the Symbolic Trajectory Evaluation technique for formal verification. Experimental results show that the new model significantly outperforms the transistor level memory model when verifying a simple pipelined data path.

Formal verification of an ARM processor

This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM processors, uses features such as a 5-stage instruction pipeline, predicated execution, forwarding logic and multi-cycle instructions. The instruction set of the processor was defined as a set of abstract assertions. An implementation mapping was used to relate the abstract states in these assertions to detailed circuit states in the gate-level implementation of the processor. Symbolic Trajectory Evaluation was used to verify that the circuit fulfills each abstract assertion under the implementation mapping. The verification was done concurrently with the design implementation of the processor. Our verification did uncover 4 bugs that were reported back to the designer.

Formal verification of a superscalar execution unit

Many modern systems are designed as a set of interconnectedreactive subsystems. The subsystem verification task is toverify an implementation of the subsystem against the simple deterministichigh-level specification of the entire system. Our verificationmethodology, based on Symbolic Trajectory Evaluation, is ableto bridge the wide gap between the abstract specification and theimplementation specific details of the subsystem. This paper presentsa detailed description of an industrial application of this methodologyto the fixed point execution unit of the PowerPC processor.We were able to verify a representative instruction under all possiblestall, bypass, pipeline conditions and under all possible timingsfor interface to other functional units in the processor.

Automatic Clock Abstraction from Sequential Circuits

Our goal is to transform a low-level circuit design into a more abstract representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equivalent gatelevel representation. This work focuses on taking that gate-level sequential circuit and performing a temporal analysis which abstracts the clocks from the circuit. The analysis generates a cycle-level gate model with the detailed timing abstracted from the original circuit. Unlike other possible approaches, our analysis does not require the user to identify state elements or give the timings of internal state signals. The temporal analysis process has applications in simulation, formal verification, and reverse engineering of existing circuits. Experimental results show a 40%-70% reduction in the size of the circuit and a 3X-150X speedup in simulation time.

Inverter minimization in multi-level logic networks

We look at the problem of inverter minimization in multi-level logic networks. The network is specified in terms of a set of base functions and the inversion operation. The library is specified as a set of allowed permutations of phase assignments on each base function. Traditional approaches to this problem have been limited to greedy heuristics based on local information. Our approach takes a more global view and maps the problem of inverter minimization into a problem of removing a minimum of vertices from a graph, so as to make the remaining graph two-colorable. This approach has the flexibility of capturing a variety of design-specific features that are relevant to the problem of inverter minimization. Although, in general the problem is NP-complete, we have developed several good heuristic and branch and bound search techniques.

Verifying Nondeterministic Implementations of Deterministic Systems

Some modern systems with a simple deterministic high-level specification have implementations that exhibit highly nondeterministic behavior. Such systems maintain a simple operation semantics at the high-level. However their underlying implementations exploit parallelism to enhance performance leading to interaction among operations and contention for resources. The deviation from the sequential execution model not only leads to nondeterminism in the implementation but creates the potential for serious design errors. This paper presents a methodology for formal verification of such systems. An abstract specification describes the high-level behavior as a set of operations. A mapping relates the sequential semantics of these operations to the underlying nondeterminism in the implementation. Symbolic Trajectory Evaluation, a modified form of symbolic simulation, is used to perform the actual verification. The methodology is currently being used to verify portions of a superscalar processor which implements the PowerPC architecture. Our initial work on the fixed point unit indicates that this is a promising approach for verification of processors.

Mapping switch-level simulation onto gate-level hardware accelerators

In this paper, we present a framework for performing switchlevel simulation on hardware accelerators. A symbolic analyzer preprocesses the MOS network into a functionally equivalent Boolean representation. The analyzer thus converts switch-level simulation into a task of evaluating Boolean expressions. Our approach maps the Boolean representation into the instruction set of the hardware accelerator. The resultant framework supports switch level simulation on a class of hardware accelerators that traditionally have been limited to gate-level simulation.

Extraction of finite state machines from transistor netlists by symbolic simulation

The paper describes a new technique for extracting clock level finite state machines (FSMs) from transistor netlists using symbolic simulation. The transistor netlist is preprocessed to produce a gate level representation of the netlist. Given specifications of the circuit clocking and input and output timing, simulation patterns are derived for a symbolic simulator. The result of the symbolic simulation and extraction process is the next state and output function of the equivalent FSM, represented as Ordered Binary Decision Diagrams. Compared to previous techniques, our extraction process yields an order of magnitude improvement in both space and time, is fully automated and can handle static storage structures and time multiplexed inputs and outputs.

Liveness vs safety: a practical viewpoint

Within the formal verification community, choosing between liveness and safety approaches has long been a subject of debate. This paper applies both approaches to a common design in the networking industry, a Deficit Weighted Round Robin (DWRR) arbiter. It then presents the tradeoffs we encountered while applying both approaches and also describes how we overcame state space explosion. We also describe two real post-silicon design bugs that we found, which were missed by all simulation methods.

Message from the Technical Program Chairs

The International Conference on VLSI Design and International Conference on Embedded Systems begins with a two-day tutorial program that showcases the latest trends in technology. The three-day technical program begins after the tutorials, and includes about nine keynote addresses by industry and academia leaders who will provide perspectives on a broad range of areas, from those that are important today to trends that will emerge over the next several decades. The core of the technical program consists of a selected set of technical papers. The conference received 310 submissions in ten subject categories, and team of 83 technical experts, led by 18 track chairs, geographically distributed over the world, evaluated these papers. Two in-person program committee meetings were held in Princeton, NJ, USA and Noida, India. After an intensively deliberative process involving the evaluation of 1289 submitted reviews and detailed discussions on each submission, 66 high-quality papers were accepted to the program. These technical papers have been arranged into a set of technical sessions scheduled in 3-parallel sessions between January 7 and 9. The contributed papers are complemented by embedded tutorials on new and emerging trends, including advanced topics in low-power computing, embedded security, design under soft errors and electrostatic discharge (ESD) effects. In parallel with the technical tracks, the Student Conference tracks is intended to motivate students to pursue careers in this area by providing them with technical content at the appropriate level, paired with panel discussions that address some of their prime concerns. New to the program this year is the User/Designer Track This track aims to bring to the conference real world experience of designing complex chips and is specifically targeted to EDA tool users and designers in the industry, and to provide a platform for the design community to present and discuss practical aspects of all stages of design, using actual chip implementations as examples. Even though this is a new effort, the response this year was very encouraging, with 64 submissions under evaluation. We expect this to be a successful and continuing component of the conference in future years.