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Dive into the research topics where Alvaro Velasquez is active.

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Featured researches published by Alvaro Velasquez.


international symposium on nanoscale architectures | 2015

Automated synthesis of crossbars for nanoscale computing using formal methods

Alvaro Velasquez; Sumit Kumar Jha

Since the fabrication of nanoscale memristors by HP Labs in 2008, there has been a sustained interest in the use of crossbars of nanoscale memristors for digital storage and neuromorphic computing. However, the same success has not been replicated in the use of crossbars for performing generalpurpose computations that can support the existing software infrastructure originally designed for von Neumann architectures. One of the fundamental challenges facing the exploitation of nanoscale memristor crossbars is the existence of sneak paths. It has been shown that sneak paths can be used to perform Boolean computations in crossbars. However, the human mind can be easily overwhelmed by the large number of sneak paths that may arise in a crossbar. It is not surprising that the size of manually-designed crossbars has been too large for practical applications. In this paper, we demonstrate how formal methods can be used to automatically synthesize compact crossbar designs that employ the sneak paths phenomena as a fundamental design primitive to evaluate Boolean formula.


international symposium on circuits and systems | 2016

Flow-based computing on nanoscale crossbars: Design and implementation of full adders

Zahiruddin Alamgir; Karsten Beckmann; Nathaniel C. Cady; Alvaro Velasquez; Sumit Kumar Jha

We present the design and implementation of a full adder circuit that exploits the natural flow of current through nanowires and More-than-Moore nano-devices in two dimensional crossbars. We evaluate the speed and energy efficiency of our design and compare it to equivalent one-bit adder designs using CMOS and nanoscale memristors. Our memristive full adder circuit has been shown to be an order of magnitude faster and more energy-efficient than equivalent CMOS designs. Our circuit is an order of magnitude more compact that equivalent CMOS designs. We also argue that our design occupies less area and is faster than competing memristor designs.


Intelligent Decision Technologies | 2014

Parallel computing using memristive crossbar networks: Nullifying the processor-memory bottleneck

Alvaro Velasquez; Sumit Kumar Jha

We are quickly reaching an impasse to the number of transistors that can be squeezed onto a single chip. This has led to a scramble for new nanotechnologies and the subsequent emergence of new computing architectures capable of exploiting these nano-devices. The memristor is a promising More-than-Moore device because of its unique ability to store and manipulate data on the same device. In this paper, we propose a flexible architecture of memristive crossbar networks for computing Boolean formulas. Our design nullifies the gap between processor and memory in von Neumann architectures by using the crossbar both for the storage of data and for performing Boolean computations. We demonstrate the effectiveness of our approach on practically important computations, including parallel Boolean matrix multiplication.


international conference on computer design | 2015

Fault-tolerant in-memory crossbar computing using quantified constraint solving

Alvaro Velasquez; Sumit Kumar Jha

There has been a surge of interest in the effective storage and computation of data using nanoscale crossbars. In this paper, we present a new method for automating the design of fault-tolerant crossbars that can effectively compute Boolean formula. Our approach leverages recent advances in Satisfiability Modulo Theories (SMT) solving for quantified bit-vector formula (QBVF). We demonstrate that our method is well-suited for fault-tolerant computation and can perform Boolean computations despite stuck-open and stuck-closed interconnect defects as well as wire faults. We employ our framework to generate various arithmetic and logical circuits that compute correctly despite the presence of stuck-at faults as well as broken wires.


international symposium on circuits and systems | 2016

Parallel boolean matrix multiplication in linear time using rectifying memristors

Alvaro Velasquez; Sumit Kumar Jha

Boolean matrix multiplication (BMM) is a fundamental problem with applications in graph theory, group testing, data compression, and digital signal processing (DSP). The search for efficient BMM algorithms has produced several fast, albeit impractical, algorithms with sub-cubic time complexity. In this paper, we propose a memristor-crossbar framework for computing BMM at the hardware level in linear time. Our design leverages the diode-like characteristics of recently studied rectifying memristors to resolve the pervasive sneak paths constraint that is ubiquitous in crossbar computing.


acm symposium on parallel algorithms and architectures | 2018

Brief Announcement: Parallel Transitive Closure Within 3D Crosspoint Memory

Alvaro Velasquez; Sumit Kumar Jha

The infamous memory-processor bottleneck has motivated the search for logic-in-memory architectures. In this paper, we demonstrate how the transitive closure problem can be solved through in-memory computing within a 3D crosspoint memory. The proposed architecture requires only two layers of 1-diode 1-resistor (1D1R) interconnects and external feedback loops.


International Symposium on Combinatorial Optimization | 2018

Finding Minimum Stopping and Trapping Sets: An Integer Linear Programming Approach

Alvaro Velasquez; K. Subramani; Steven Drager

In this paper, we discuss the problems of finding minimum stopping sets and trapping sets in Tanner graphs, using integer linear programming. These problems are important for establishing reliable communication across noisy channels. Indeed, stopping sets and trapping sets correspond to combinatorial structures in information-theoretic codes which lead to errors in decoding once a message is received. We present integer linear programs (ILPs) for finding stopping sets and several trapping set variants. In the journal version of this paper, we prove that two of these trapping set problem variants are NP-hard for the first time. The effectiveness of our approach is demonstrated by finding stopping sets of size up to 48 in the (4896, 2474) Margulis code. This compares favorably to the current state-of-the-art, which finds stopping sets of size up to 26. For the trapping set problems, we show for which cases an ILP yields very efficient solutions and for which cases it performs poorly. The proposed approach is applicable to codes represented by regular and irregular graphs alike.


international symposium on circuits and systems | 2017

Computation of Boolean matrix chain products in 3D ReRAM

Alvaro Velasquez; Sumit Kumar Jha

Energy concerns, the infamous memory wall, and the enormous data deluge of the current big-data age have made the integration of processing and memory elements into a very appealing paradigm. In this paper, we focus on a computation-in-memory solution to the problem of multiplying a set of Boolean matrices, also known as Boolean matrix chain multiplication (BMCM). This is a fundamental computational task with applications in graph theory, group testing, data compression, and digital signal processing. In particular, we propose a framework for mapping arbitrary instances of BMCM to a 3-dimensional (3D) crossbar memory architecture consisting of 1-diode 1-resistor (1D1R) structures.


network computing and applications | 2016

The cardinality-constrained paths problem: Multicast data routing in heterogeneous communication networks

Alvaro Velasquez; Piotr J. Wojciechowski; K. Subramani; Steven Drager; Sumit Kumar Jha

In this paper, we present two new problems and a theoretical framework that can be used to route information in heterogeneous communication networks. These problems are the cardinality-constrained and interval-constrained paths problems and they consist of finding paths in a network such that cardinality constraints on the number of nodes belonging to different sets of labels are satisfied. We propose a novel algorithm for finding said paths and demonstrate the effectiveness of our approach on networks of various sizes.


international conference on computational advances in bio and medical sciences | 2014

Putting humpty-dumpty together: Mining causal mechanistic biochemical models from big data

Faraz Hussain; Alvaro Velasquez; Emily Sassano; Sumit Kumar Jha

In traditional engineering disciplines, the construction of a system is usually preceded by a formal or informal specification of the design of the system being developed. In biochemical applications, however, a detailed specification of the systems structure and dynamics is usually unavailable. Thus, mechanistic details of biochemical systems must be mined from experimental observations. In this paper, we adopt a formal methods approach towards deriving causal mechanistic models from time-series observations of biochemical systems. The mined model captures causality among multiple biological events and also allows causal relationships between sets of events. We exploit results from trace theory and use the power of powerful constraint solvers to develop a new framework for causality identification and reasoning that captures dynamic relationships among species in biochemical reaction networks.

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Sumit Kumar Jha

University of Central Florida

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Faraz Hussain

University of Central Florida

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K. Subramani

West Virginia University

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Steven Drager

Air Force Research Laboratory

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Dilia E. Rodriguez

University of Central Florida

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Emily Sassano

University of Central Florida

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Karsten Beckmann

State University of New York System

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Nathaniel C. Cady

State University of New York System

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