Karsten Beckmann

Flow-based computing on nanoscale crossbars: Design and implementation of full adders

We present the design and implementation of a full adder circuit that exploits the natural flow of current through nanowires and More-than-Moore nano-devices in two dimensional crossbars. We evaluate the speed and energy efficiency of our design and compare it to equivalent one-bit adder designs using CMOS and nanoscale memristors. Our memristive full adder circuit has been shown to be an order of magnitude faster and more energy-efficient than equivalent CMOS designs. Our circuit is an order of magnitude more compact that equivalent CMOS designs. We also argue that our design occupies less area and is faster than competing memristor designs.

Techniques for Improved Reliability in Memristive Crossbar PUF Circuits

Hardware security has emerged as an important field of study aimed at mitigating issues such as integrated circuit (IC) piracy and counterfeiting. One popular solution for such hardware security attacks are physically unclonable functions (PUF) which provide a hardware specific unique identification based on intrinsic process variations within individual integrated circuit implementations. At the same time, as technology scaling progresses further into the nanometer region, emerging nanoelectronic technologies such as memristors become viable options. Several examples of nanoelectronic memristor-based PUF circuits have been proposed in the last few years. In this paper, we analyze the behavior of crossbar memristive PUF circuits under different environmental conditions such as varying temperature, supply rail voltage fluctuations and aging. We also present an approach that improves the reliability of these circuits, taking environmental variations into consideration. The advantages and challenges associated with these PUFs are also discussed in detail. Specifically, we show results for security metrics including reliability, uniqueness and uniformity. These security performance results are presented alongside estimates for power, area and delay showing the advantages of using nanoelectronic PUFs from the perspective of efficient resource utilization.

An extendable multi-purpose 3D neuromorphic fabric using nanoscale memristors

Neuromorphic computing offers an attractive means for processing and learning complex real-world data. With the emergence of the memristor, the physical realization of cost-effective artificial neural networks is becoming viable, due to reduced area and increased performance metrics than strictly CMOS implementations. In the work presented here, memristors are utilized as synapses in the realization of a multi-purpose heterogeneous 3D neuromorphic fabric. This paper details our in-house memristor and 3D technologies in the design of a fabric that can perform real-world signal processing (i.e., image/video etc.) as well as everyday Boolean logic applications. The applicability of this fabric is therefore diverse with applications ranging from general-purpose and high performance logic computing to power-conservative image detection for mobile and defense applications. The proposed system is an area-effective heterogeneous 3D integration of memristive neural networks, that consumes significantly less power and allows for high speeds (3D ultra-high bandwidth connectivity) in comparison to a purely CMOS 2D implementation. Images and results provided will illustrate our state of the art 3D and memristor technology capabilities for the realization of the proposed 3D memristive neural fabric. Simulation results also show the results for mapping Boolean logic functions and images onto perceptron based neural networks. Results demonstrate the proof of concept of this system, which is the first step in the physical realization of the multi-purpose heterogeneous 3D memristive neuromorphic fabric.

A practical hafnium-oxide memristor model suitable for circuit design and simulation

This paper proposes a practical polynomial model for HfO2 memristor fabricated in-house at SUNY Polytechnic Institute. Although there is no shortage of memristor models in the literature, most models are not general and assume specific switching and conduction mechanisms. This is often deemed impractical for circuit designers who wish to develop a model for a specific technology of interest. Thus, circuit designers have sought empirical models that are easily fit to their specific device. The model should be simple, intuitive, and most importantly, fast to converge. The proposed model is based on measurable parameters and matches the experimental data well. The convergence of our model is tested against other models in the literature and shows comparable results. It is also shown that the smoothness of the model around the memristor threshold is critical for fast convergence time.

Performance Enhancement of a Time-Delay PUF Design by Utilizing Integrated Nanoscale ReRAM Devices

Currently the semiconductor industry is in search of a Physically-Unclonable-Function (PUF) implementation, which combines high reliability and uniqueness with low area and power consumption. The characteristics of emerging nanoscale Resistive Random Access Memory (ReRAM) devices fulfill most of these properties, as they exhibit inherent variability with low area consumption. Of particular interest is that the resistive states of ReRAM devices show a strong dependence on the distribution of grain boundaries within the device, which leads to variability in total device resistance. In this work we transform the classic CMOS time-delay PUF (TD-PUF) utilizing integrated nanoscale ReRAM devices to achieve better performance metrics including uniqueness and reliabilitiiy. The enhanced design exploits the property of high resistance variability of ReRAMs for the design of a ReRAM based delay stage that exhibits excellent uniqueness. Accurate simulation and characterization of the proposed PUF was achieved by extracting resistance values, temperature dependence and usage stress of ReRAM devices fabricated in-house and their application in the proposed TD-PUF are discussed. A 24 stage time-delay PUF utilizing 48 ReRAM devices was simulated and results show excellent reliability with respect to environmental parameters. A temperature range of 0 to 125°C was simulated and an optimum reliability was observed at 0.79 V. A supply voltage noise of ±30 mV had no impact on the uniqueness and reliability. The proposed design was compared against two pure CMOS implementations of a TD-PUF. The comparison was performed with respect to the aforementioned metrics and under the same environmental conditions, showing up to 5 times increase in performance.

Reliability of fully-integrated nanoscale ReRAM/CMOS combinations as a function of on-wafer current control

Resistive random access memory (ReRAM) is a novel form of non-volatile memory expected to replace FLASH memory in the near future. As a further step toward use of ReRAM in computer architectures, we have developed a CMOS/ReRAM hybrid process, integrating ReRAM into a CMOS process flow. In this study, we investigate yield, reliability, endurance, threshold voltages (forming, set and reset voltages) of ReRAM devices implemented in the back end of the line (BEOL). The focus of this study is on single ReRAM devices operated with an external transistor (1T1R configuration). Yield and endurance of these 1T1R configured devices show a strong dependence on device position on the wafer, the device size, and the current compliance used during the initial forming and subsequent set sweeps. Elevated temperatures resulted in a shift of the optimum operation conditions and could be used to improve device performance. Variance in performance of the ReRAM devices was directly correlated with manufacturing issues and material properties to gain maximum information for future improvements.

Comparison of random telegraph noise, endurance and reliability in amorphous and crystalline hafnia-based ReRAM

Resistive random access memory (ReRAM) is a novel form of non-volatile memory expected to replace FLASH memory in the near future. To optimize the switching parameters of ReRAM we investigated fab-friendly HfOx based devices with an either amorphous or crystalline active layers. Our devices are fabricated with a copper bottom electrode, a 50 nm sub-stoichiometric hafnia layer, and a platinum top electrode. These devices operate according to the electrochemical metallization model. We compared endurance, reliability and random telegraph noise (RTN) with pulse-based cycling/readout. Initial endurance measurements show 4 million and 70 million consecutive cycles for the amorphous and crystalline hafnia, respectively. The transmission rate was shown to be slightly higher for the amorphous active layer with a confidence of 85%. Furthermore, it is shown that the relative difference in resistance during RTN is not dependent on the crystallinity, but increases with an increase in high resistive state. A high variety of noise patterns were observed, including transition rates from 1 s-1 up to 12000 s-1 and multi-state traps.

Pulse width and height modulation for multi-level resistance in bi-layer TaOx based RRAM

Mutli-level switching in resistive memory devices enables a wide range of computational paradigms, including neuromorphic and cognitive computing. To this end, we have developed a bi-layer tantalum oxide based resistive random access memory device using Hf as the oxygen exchange layer. Multiple, discrete resistance levels were achieved by modulating the RESET pulse width and height, ranging from 2 kΩ to several MΩ. For a fixed pulse height, OFF state resistance was found to increase gradually with the increase in the pulse width, whereas for a fixed pulse width, the increase in the pulse height resulted in drastic changes in resistance. Resistive switching in these devices transitioned from Schottky emission in the OFF state to tunneling based conduction in the ON state, based on I-V curve fitting and temperature dependent current measurements. These devices also demonstrated endurance of more than 108 cycles with a satisfactory Roff/Ron ratio and retention greater than 104 s.

Design Considerations for Memristive Crossbar Physical Unclonable Functions

Hardware security has emerged as a field concerned with issues such as integrated circuit (IC) counterfeiting, cloning, piracy, and reverse engineering. Physical unclonable functions (PUF) are hardware security primitives useful for mitigating such issues by providing hardware-specific fingerprints based on intrinsic process variations within individual IC implementations. As technology scaling progresses further into the nanometer region, emerging nanoelectronic technologies, such as memristors or RRAMs (resistive random-access memory), have become interesting options for emerging computing systems. In this article, using a comprehensive temperature dependent model of an HfOx (hafnium-oxide) memristor, based on experimental measurements, we explore the best region of operation for a memristive crossbar PUF (XbarPUF). The design considered also employs XORing and a column shuffling technique to improve reliability and resilience to machine learning attacks. We present a detailed analysis for the noise margin and discuss the scalability of the XbarPUF structure. Finally, we present results for estimates of area, power, and delay alongside security performance metrics to analyze the strengths and weaknesses of the XbarPUF. Our XbarPUF exhibits nearly ideal (near 50%) uniqueness, bit-aliasing and uniformity, good reliability of 90% and up (with 100% being ideal), a very small footprint, and low average power consumption ≈104μW.