Amanpal Singh

Dielectric Anomaly in Mg Doped ZnO Thin Film Deposited by Sol–Gel Method

Magnesium doped ZnO Zn0.75Mg0.25O polycrystalline thin film was deposited on p-type Si by sol–gel method, and the same was annealed at 1000°C in oxygen rich environment. The magnesium doping in lattice structure of zinc oxide was examined by X-ray diffraction measurements. The dielectric phase transition observed at 378 K indicated the existence of ferroelectric properties in the deposited film. The ferroelectricity in the deposited film was confirmed by the polarization and electric field hysteresis curve. Maximum values of the spontaneous polarization and coercive field were found to be 0.29 C/cm2 and 18 kV/cm, respectively. The clockwise rotation in capacitance and voltage hysteresis loop of the deposited film on p-type Si indicated that the charge compensation on the Si surface was induced by the ferroelectric polarization. The grain size and microstructure were analyzed by atomic force microscopy.

Band offset measurements in Zn1−x Sb x O/ZnO hetero-junctions

Accurate knowledge of the alignment of conduction and valence bands of layers at the heterojunction and warrant knowledge of the band offsets at the interface is essential for Zn1−x Sb x O/ZnO based quantum well device designing and modeling. Under this scenario, valence band offsets of Zn1−x Sb x O/ZnO heterostructures grown by the pulsed laser deposition technique was measured by photoelectron spectroscopy and consequently, the conduction band offset was calculated by UV-visible spectroscopy. The change in band alignment has been observed with the dopant (Sb) concentration. Ratios of conduction band offset to valence band offset were estimated to be 1.67 and 0.04 for x = 0.03 and 0.06, respectively, for Sb doped films. A Type-II band alignment was observed at the Zn0.97Sb0.03O/ZnO interface, whereas the Type-I band alignment took place at the Zn0.94Sb0.06O/ZnO interface.

Deposition of ZnO ultrathin films by sol-gel route

Crack free, uniform and high quality ultrathin films (~ 2-3 nm) of zinc oxide were achieved by cost effective and simplest wet chemical sol-gel route. The films were deposited at different spinning speed (1500 to 6000 rpm) on the silicon substrates. The average thickness per layer for each sample was measured by using surface profiler. The thickness of the film is reduced linearly with the spinning speed but the uniformity of the films was degraded for deposition at higher RPM (≤ 3500). The uniformity of deposited layers was observed by Photoluminescence mapping and it was found that the cracks density enhanced for higher spinning. In AFM images for the deposited films the grains were appeared with outlying distribution and the average grain size was increased with spinning speed. The films possessed high uniformity with lowest thickness (~ 5 nm) at 3000 rpm. Further reduction in thickness was achieved by decreasing the concentration of zinc in the prepared sol. It was observed that the films were still smooth but the thickness extensively reduced up to 2 nm. The effect of substrate size on the quality of thin film also observed. To study this effect the films were deposited on 1 × 1, 2 × 2, 3 × 3 and 5 × 5 cm2 substrates at 3000 rpm. It was observed by PL mapping that for substrates with large area the density of cracks was enhanced.

Deposition and characterization of amorphous electroless Ni-Co-P alloy thin film for ULSI application

Electroless based Ni-Co-P alloy thin films were deposited using sodium hypophosphite as a reducing agent and sodium citrate as a complexing agent in an alkaline plating bath. The effect of solution pH and temperature on the plating rate was examined. The decrease in activation energy (81.35 − 73.54 kJ mole−1) for the Ni-Co-P thin films deposited on corning glass was observed with the increase in pH (8.5–9.38) of the plating bath. There is a significant decrease in sheet resistance of alloy thin films as the post deposition annealing temperature approaches 400 °C. The presence of nickel as well as nickel phosphide peaks and transition from metastable Ni12P5, Ni8P5 and Ni5P2 phases into thermodynamically stable NiP, NiP2, Ni3P phases after annealing at 600 °C was observed in XRD spectra, indicating the crystallization of the thin films. Surface topography analysis shows the variation of grain size in the range 20–40 nm.

Near edge X-ray absorption fine structure study of Zn0.8Mg0.2O thin films

We report the local electronic structure study of Zn0.8Mg0.2O thin films using x-ray absorption spectroscopy. The films were deposited on p-Si (100) substrates by sol-gel method and then annealed in O2 ambient for 1 hour. X-ray diffraction (XRD) confirmed the single phase wurtzite structure with a (002) preferred orientation. The near edge x-ray absorption fine structure (NEXAFS) spectrum collected at O K–edge indicates the presence of some oxygen vacancies in the film. The NEXAFS at Mg K-edge confirms the Mg doping into ZnO lattice. Zn L3-edge spectra feature reflects no Zn defect related features.

Deposition and evaluation of self assembled monolayer as diffusion barrier for copper metallization for integrated circuits

Self Assembled Monolayer was deposited on silicon substrate using 3-aminopropyltrimethoxysilane (APTMS). The diffusion barrier properties of this layer against copper diffusion were studied. For this purpose, Cu/SiO2/Si and Cu/SAM/SiO2/Si structures were compared. The samples were annealed at various temperatures in vacuum ambient. The characterization was performed using X-Ray diffraction, Four Probe Resistivity measurement and Capacitance-Voltage technique. C-V measurement was performed by applying Bias Thermal Stress (BTS). XRD Results indicated that combination of SiO2/SAM worked as diffusion barrier layer up to 600 °C whereas SiO2 could work as barrier only up to 400 °C. C-V and resistivity plots also supported the possibility of using SAM as a good barrier for copper metallization in VLSI systems.Self Assembled Monolayer was deposited on silicon substrate using 3-aminopropyltrimethoxysilane (APTMS). The diffusion barrier properties of this layer against copper diffusion were studied. For this purpose, Cu/SiO2/Si and Cu/SAM/SiO2/Si structures were compared. The samples were annealed at various temperatures in vacuum ambient. The characterization was performed using X-Ray diffraction, Four Probe Resistivity measurement and Capacitance-Voltage technique. C-V measurement was performed by applying Bias Thermal Stress (BTS). XRD Results indicated that combination of SiO2/SAM worked as diffusion barrier layer up to 600 °C whereas SiO2 could work as barrier only up to 400 °C. C-V and resistivity plots also supported the possibility of using SAM as a good barrier for copper metallization in VLSI systems.

Synthesis and characterization of graphene thin film by thermal reduction

Graphene thin film has been synthesize by thermal reduction of graphene oxide (GO) formed by modified Hummer’s method. GO solution was prepared in DI water and subsequently deposited on the SiO2/Si substrate by spin casting at 2000rpm. The prepared samples were thermally reduced at different temperature in vacuum. The XRD results confirms the reduction of GO. Four probe conductivity measurement technique was used for the conductivity measurement.