Amaresh V. Malipatil

A 1.0625

A 14.025 Gb/s multi-media transceiver employs on-die Rx AC coupling with baseline wander correction and equalizes up to 26 dB insertion loss at 14.025 Gb/s with a linear equalizer, 10-tap DFE, and 4-tap Tx FIR filter in SST driver. The proposed techniques enable direct feedback for 1st-tap ISI cancellation, and positions of four DFE taps to be adapted over the range of 7 to 38 UI. The prototype is realized in 40 nm CMOS, consumes 410 mW at worst case, and has passed 16GFC compliance tests at 14.025 Gb/s.

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This paper presents a 28 Gb/s multistandard SerDes macro which is fabricated in TSMC 28 nm CMOS process. The transimpedance amplifier (TIA) base analog front-end achieved 15 dB high-frequency boost with an on-chip compact passive inductor. The adaptation loop for the boost is decoupled from the decision feedback equalizer (DFE) adaptation by the use of a group delay algorithm. The DFE is a half-rate 1-tap unrolled design with only two total error latches for power and area reduction. A two-stage sense amplifier-based latch achieved sensitivity of 15 mV. The high-speed clock buffer uses a PMOS active inductor circuit with common-mode feedback to optimize the circuit performance. The transceiver achieves error-free operation at 28 Gbps with 34 dB channel loss, consumes the worst case power of 560 mW/lane, and fully complies with multiple standards and applications.

14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS

This paper proposes adaptation algorithms for adapting a class of practical continuous time equalizer architectures. Gradient equations used to adapt the equalizer are derived based on impulse response weights related to the equalizer. A simplified version of the gradient is proposed. Simulation results across a range of real backplane channels show proper convergence of the gradients and minimal performance loss for the simplified gradient.

2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS

This paper proposes a class of downsampled floating tap decision feedback equalization (DFE) architectures based on downsampling of the floating tap positions. The architectures offer significant complexity and power reduction compared with a standard floating tap DFE architecture with minimal loss in performance. Simulation results with realistic channel models are used to validate the performance of these architectures.

Adaptation algorithms for a class of continuous time analog equalizers with application to serial links

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A class of downsampled floating tap DFE architectures with application to serial links

This paper proposes a power/area efficient method for realizing a class of downsampled floating tap decision feedback equalization (DFE) architectures for serial links. The architectures offer significant complexity and power reduction over a standard floating tap DFE architecture with minimal performance loss. A shift register multi-phase clock based design in 28 nm CMOS is implemented for operation at 28.05 Gb/s. At 28.05 Gb/s, the designed downsampled architecture dissipates only 67% of the power of the corresponding standard architecture operating at 17 Gb/s. At the lower 17 Gb/s speed, the downsampled architecture dissipates only 45% of the power of the standard architecture.